Testing CPU Emulators
PaperFirst seen 6/7/2026
Last seen 6/7/2026
Evidence 11 chunks
NEIGHBORHOOD
No graph connections found for this entity yet. It may appear in future ingestion runs.
explore full graph →RELATIONSHIPS
17 connectionsThe paper discusses instruction encoding as a key aspect of generating valid test-cases.
The paper evaluates Valgrind as one of four IA-32 emulators tested.
The paper evaluates Pin as one of four IA-32 emulators tested.
The paper formally introduces the notion of faithful emulation as the basis for its testing methodology.
The paper discusses exception handling as part of the testing methodology and defects found in emulators.
The paper compares random test-case generation with CPU-assisted test-case generation in terms of instruction coverage.
The paper mentions Simics as an example of a whole-system emulator.
The paper introduces EmuFuzzer, a prototype implementation of the testing methodology for IA-32 emulators.
The paper presents a testing methodology based on fuzzing for CPU emulators.
The paper evaluates QEMU as one of four IA-32 emulators tested.
The paper evaluates BOCHS as one of four IA-32 emulators tested.
The paper Testing CPU Emulators is authored by Roberto Paleari.
The paper Testing CPU Emulators is authored by Giampaolo Fresi Roglia.
The paper Testing CPU Emulators is authored by Danilo Bruschi.
The paper mentions the Church-Turing thesis to justify that any hardware system can be emulated via software.
The paper mentions CISC architectures as having a rich instruction set that makes emulator development challenging.
The paper Testing CPU Emulators is authored by Lorenzo Martignoni.