exception handling

Concept

Exception handling is a cross-cutting computing concept that covers hardware-level CPU exception behavior, programming-language error handling constructs, and generated assembly program sections. The provided evidence documents exception handling in three distinct contexts: CPU emulator testing methodology (with documented defects in Pin, Valgrind, QEMU, and BOCHS), software-engineering studies of exception flows and anti-patterns in Java and C# codebases, and the CHIPS Alliance `riscv-dv` assembly generator's emission of exception-handler sections for RISC-V processor verification.

First seen 5/27/2026

Last seen 6/7/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

Exception handling is a concept that spans multiple layers of computing, from hardware CPU behavior to high-level programming-language constructs. The provided evidence touches on exception handling in three distinct contexts: (i) CPU emulator testing, where exceptions are modeled as part of the abstract machine state and used to detect emulation defects; (ii) programming-language practices, where studies have examined exception flows and anti-patterns in Java and C# codebases; and (iii) RISC-V assembly program generation, where the riscv-dv random instruction generator emits a dedicated exception-handling section.

Exception Handling in CPU Emulators

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RELATIONSHIPS

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Testing CPU Emulators ← mentions 100% 2e

The paper discusses exception handling as part of the testing methodology and defects found in emulators.

gen_section ← implements 1e

gen_section selects and implements exception handling instructions in the generated program.

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Testing CPU Emulators MENTIONS Extracted graph relationship

CITATIONS

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11 citations — click to expand

[1] The CPU abstract machine state is modeled as s = (pc, R, M, E), where E is the exception state taking values from {⊥, illegal instruction, division by zero, general protection fault, ...} and ⊥ indicates no exception. Testing CPU Emulators

[2] Pin does not properly handle trap and illegal-instruction exceptions and does not notify the emulated program; several legal instructions that raise a general-protection fault on the physical CPU are executed without generating any exception on Pin. Testing CPU Emulators

[3] On Valgrind (and QEMU), instructions are not executed atomically; when an exception occurs mid-instruction, the state of memory and registers may differ from the state prior to the instruction's execution, which is an atomicity defect relative to the physical CPU. Testing CPU Emulators

[4] In EmuFuzzer, page-fault and other exceptions are intercepted to drive test-case execution and lazy memory synchronization; execution terminates on (i) reaching the last instruction, (ii) a missing-page page fault, (iii) a non-writable-page write page fault, or (iv) any other exception. Testing CPU Emulators

[5] The EmuFuzzer methodology embeds code in the emulator under analysis that intercepts the beginning and end of each basic block (or instruction), intercepts exceptions, and provides an interface to register and memory state. Testing CPU Emulators

[6] A 2017 case study on 16 open-source Java and C# libraries found that each try block has up to 12 possible potentially recoverable yet propagated exceptions, and 22% of distinct possible exceptions trace back to multiple methods (average 1.39, max 34). Revisiting Exception Handling Practices with Exception Flow Analysis

[7] The 2017 exception-flow analysis study noted a lack of documentation of possible exceptions and their sources, and observed different exception-handling strategies between Java and C#. Revisiting Exception Handling Practices with Exception Flow Analysis

[8] A 2017 anti-patterns study identified commonly occurring exception-handling anti-patterns as Unhandled Exceptions, Catch Generic, Unreachable Handler, Over-catch, and Destructive Wrapping, with prevalence differences between C# and Java. Studying the Prevalence of Exception Handling Anti-Patterns

[9] The `riscv-dv` `riscv_asm_program_gen` class generates a complete RISC-V assembly program with multiple sections including initialization, instruction, data, stack, page table, interrupt handling, and exception handling. RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator

[10] After main and subprogram generation, host-interface instructions are added via `gen_section` with labels `write_tohost` and `_exit`; `push_gpr_to_kernel_stack()` pushes general-purpose registers to the stack for trap handling. RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator

[11] `riscv_asm_program` uses `gen_section()` to select the instruction string `mtvec_handler`, which contains `exception_handler` and `interrupt_handler` definitions. RISC-V source class riscv_asm_program_gen, the brain behind assembly instruction generator