Code Generation for Custom Architectures using Constraint Programming
PaperFirst seen 6/9/2026
Last seen 6/9/2026
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40 nodes · 64 edgesgraph · Code Generation for Custom Architectures using Constraint Programming · depth=1
RELATIONSHIPS
39 connectionsThe thesis addresses automatic code generation for custom architectures.
Data assignment is addressed in the thesis as a key subproblem of code generation.
Integer linear programming is mentioned as an alternative approach to constraint programming for code generation.
Register allocation is discussed and used within the code generation framework.
Modulo scheduling is used as an additional set of constraints for loop scheduling in the thesis.
The code generation framework uses intermediate representations as input to the back end.
The thesis uses constraint programming as the core paradigm for modeling code generation problems.
VLIW architectures are mentioned in the context of related code generation work.
The thesis targets and evaluates code generation for the ePUMA architecture.
The thesis targets and evaluates code generation for the EIT architecture.
Global constraints are used extensively throughout the thesis for modeling code generation.
The cumulative global constraint is used for VLIW and SIMD groupings in scheduling.
Data assignment is modeled as non-overlapping rectangles using the diff2 global constraint.
Macro-SIMDization is mentioned as a related approach for streaming applications.
Micro-SIMDization is the approach taken in the thesis for kernel-level SIMD code generation.
Polyhedral compilation is mentioned as a related technique used by other approaches.
Superblock instruction scheduling is discussed in the related work section.
Dynamic programming is mentioned as used by related work for combined instruction selection and scheduling.
Subgraph isomorphism is mentioned as used by Unison for instruction selection.
Directed acyclic graphs are used to represent application basic blocks in code generation.
Coarse-grained reconfigurable architectures are mentioned in the context of modulo scheduling.
Stream graph scheduling is mentioned in the context of modulo scheduling for embedded systems.
Unison is mentioned as a related integrated code generation project.
Application-set driven architecture exploration is a topic covered in one of the included papers.
IDCT is mentioned as an example of a complex instruction implemented in the ePUMA architecture.
The doctoral thesis is authored by Mehmet Ali Arslan.
Krzysztof Kuchcinski supervised the thesis and is acknowledged.
The thesis was published by the Department of Computer Science, Lund University.
Instruction selection is one of the code generation subproblems addressed in the thesis.
Instruction scheduling is one of the code generation subproblems addressed in the thesis.
JaCoP is used as the constraint solver framework throughout the thesis.
The diff2 global constraint is used to model data assignment as non-overlapping rectangles.
Search space heuristics are employed to guide the constraint solver.
Branch-and-bound is used as a technique to search for optimal solutions in the constraint programming framework.
Pareto points are used in the architecture exploration paper included in the thesis.
Lifetime analysis is used to determine when data is live for data assignment.
Permutation vector optimization is addressed as a custom memory problem for SIMD architectures.
Loop unrolling is used in combination with modulo scheduling in the thesis.
A domain specific language is used as a higher-level programming interface in one of the included papers.