Coarse-Grained Reconfigurable Architecture

Concept

A Coarse-Grained Reconfigurable Architecture (CGRA) is a class of reconfigurable computing system whose processing elements operate on wide data words (e.g., ALU-level operands) rather than at the bit level, with the configuration of an array of processing elements and their interconnect being changeable to map different computations onto the same hardware. CGRAs are studied as a post-Moore alternative that aims to balance high performance with flexibility and programmability, and they are a common target for code-generation research, including constraint-programming-based approaches.

First seen 6/9/2026

Last seen 6/9/2026

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Coarse-Grained Reconfigurable Architecture

Overview

A Coarse-Grained Reconfigurable Architecture (CGRA) is a class of reconfigurable computing system whose functional units operate on wide data words (e.g., integer/ALU-level operands) rather than on single bits, distinguishing it from fine-grained FPGA-style fabrics. A CGRA typically consists of an array of processing elements (PEs) connected by a reconfigurable interconnection network; by changing the configuration of PEs and their routing, different computations can be mapped onto the same hardware.

Motivation and Design Goals

CGRAs are positioned to satisfy two competing goals: high performance and flexibility. With the end of both Dennard scaling and Moore's law, CGRAs have gained attention as a practical post-Moore alternative that retains much of the performance potential of specialized hardware while remaining programmable. A 2020 survey of the CGRA landscape summarized nearly three decades of literature on the subject and identified CGRAs as a way to "strike a balance between performance and programmability."

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Code Generation for Custom Architectures using Constraint Programming ← mentions 80% 1e

Coarse-grained reconfigurable architectures are mentioned in the context of modulo scheduling.

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CITATIONS

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[1] CGRAs are studied as a post-Moore alternative that aims to strike a balance between performance and programmability. A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

[2] A 2020 survey summarized nearly three decades of CGRA literature and compiled metrics of available CGRAs, identifying open research opportunities in array size, functionality, parallel programming-model support, and evaluation of more complex applications for HPC. A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective

[3] CGRAs aim to achieve both high performance and flexibility, and existing reconfigurable array architectures can over-provision resources without considering the specific application domain. Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

[4] Functional resources with long latency and/or large area can be pipelined and/or shared among processing elements in a CGRA template, reducing hardware cost and delay without performance degradation for the target application domain, and yielding a more efficient design in both performance and area than existing reconfigurable architectures. Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization

[5] Mei et al. introduced modulo scheduling to CGRAs to exploit loop-level parallelism. Arslan, Mehmet Ali (PhD thesis) — Related Work

[6] Kim et al. addressed long compile times for modulo scheduling on CGRAs caused by the difficulty of finding a good routing of operands through the processing elements; their patternized routes achieve approximately 6000× faster compilation while preserving on average ~70% of the throughput of the state-of-the-art. Arslan, Mehmet Ali (PhD thesis) — Related Work

[7] Constraint-programming-based code-generation approaches treat modulo scheduling as a set of additional constraints that interact with other code-generation subproblems (instruction selection, register/memory allocation) rather than as the core scheduling method, and CGRAs are mentioned as a target architecture class for such unified approaches. Arslan, Mehmet Ali (PhD thesis) — Related Work