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Coarse-Grained Reconfigurable Architecture

Concept WIKI v1 · 6/9/2026

A Coarse-Grained Reconfigurable Architecture (CGRA) is a class of reconfigurable computing system whose processing elements operate on wide data words (e.g., ALU-level operands) rather than at the bit level, with the configuration of an array of processing elements and their interconnect being changeable to map different computations onto the same hardware. CGRAs are studied as a post-Moore alternative that aims to balance high performance with flexibility and programmability, and they are a common target for code-generation research, including constraint-programming-based approaches.

Coarse-Grained Reconfigurable Architecture

Overview

A Coarse-Grained Reconfigurable Architecture (CGRA) is a class of reconfigurable computing system whose functional units operate on wide data words (e.g., integer/ALU-level operands) rather than on single bits, distinguishing it from fine-grained FPGA-style fabrics. A CGRA typically consists of an array of processing elements (PEs) connected by a reconfigurable interconnection network; by changing the configuration of PEs and their routing, different computations can be mapped onto the same hardware.

Motivation and Design Goals

CGRAs are positioned to satisfy two competing goals: high performance and flexibility. With the end of both Dennard scaling and Moore's law, CGRAs have gained attention as a practical post-Moore alternative that retains much of the performance potential of specialized hardware while remaining programmable. A 2020 survey of the CGRA landscape summarized nearly three decades of literature on the subject and identified CGRAs as a way to "strike a balance between performance and programmability."

A complementary motivation comes from reducing hardware cost: many existing reconfigurable array architectures are designed generically and therefore provision more resources than a specific application domain actually requires.

Domain-Specific Optimization

A recurring line of CGRA work focuses on tailoring the architecture template to a specific application domain. Functional resources that exhibit long latency and/or large area can be pipelined and/or shared among the processing elements, so that hardware cost and delay are reduced without performance degradation for the chosen domain. Experimental results in the literature report that such an approach is much more efficient in both performance and area than existing generic reconfigurable architectures.

Compilation Challenges

Mapping computations onto a CGRA — and in particular loop kernels — is typically formulated as a modulo scheduling problem. Two specific issues are documented in the related work on constraint-programming-based code generation:

  1. Applying modulo scheduling to CGRAs. Mei et al. introduced modulo scheduling techniques for CGRAs in order to exploit loop-level parallelism on the reconfigurable array.
  2. Long compile times caused by operand routing. Kim et al. observed that a major source of long compile times for CGRA modulo scheduling is the difficulty of finding a good routing of operands through the processing elements. They proposed patternized routes to simplify the routing problem, reporting approximately 6000× faster compilation while preserving on average ~70% of the throughput of the state-of-the-art.

In contrast, unified code-generation approaches built on constraint programming tend to treat modulo scheduling as a set of additional constraints that interact with other subproblems (instruction selection, register/memory allocation), rather than as the core scheduling engine.

Code Generation for CGRAs

CGRA code generation is closely related to instruction scheduling, register allocation, and operand routing, and these subproblems are often combined. The paper "Code Generation for Custom Architectures using Constraint Programming" explicitly mentions CGRAs among the target architectures considered, reflecting their relevance as a benchmark for unified, constraint-based compiler back ends.

Research Landscape and Open Opportunities

The 2020 performance-perspective survey compiled metrics of available CGRAs and analyzed their performance properties, with a particular focus on suitability for high-performance computing (HPC). The survey identified open research opportunities in:

  • the size of the reconfigurable array,
  • the functionality supported by processing elements,
  • support for parallel programming models, and
  • the evaluation of more complex applications.

These findings suggest ample opportunity for further CGRA research specialized towards HPC workloads.

Key Takeaways

  • CGRAs operate at the arithmetic/word level on an array of processing elements with reconfigurable interconnect.
  • They are motivated as a post-Moore compromise between the performance of specialized hardware and the flexibility of software.
  • Domain-specific resource sharing and pipelining can reduce area and delay without performance loss.
  • Modulo scheduling is the dominant compilation paradigm, with operand routing being the principal compile-time bottleneck; patternized routes offer large speedups at modest throughput cost.
  • Constraint-programming-based unified code generation treats CGRAs as a target alongside instruction selection and register allocation.

LINKED ENTITIES

1 links
Code Generation for Custom Architectures using Constraint Programming MENTIONS

CITATIONS

7 sources
7 citations
[1] CGRAs are studied as a post-Moore alternative that aims to strike a balance between performance and programmability. A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective
[2] A 2020 survey summarized nearly three decades of CGRA literature and compiled metrics of available CGRAs, identifying open research opportunities in array size, functionality, parallel programming-model support, and evaluation of more complex applications for HPC. A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective
[3] CGRAs aim to achieve both high performance and flexibility, and existing reconfigurable array architectures can over-provision resources without considering the specific application domain. Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
[4] Functional resources with long latency and/or large area can be pipelined and/or shared among processing elements in a CGRA template, reducing hardware cost and delay without performance degradation for the target application domain, and yielding a more efficient design in both performance and area than existing reconfigurable architectures. Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization
[5] Mei et al. introduced modulo scheduling to CGRAs to exploit loop-level parallelism. Arslan, Mehmet Ali (PhD thesis) — Related Work
[6] Kim et al. addressed long compile times for modulo scheduling on CGRAs caused by the difficulty of finding a good routing of operands through the processing elements; their patternized routes achieve approximately 6000× faster compilation while preserving on average ~70% of the throughput of the state-of-the-art. Arslan, Mehmet Ali (PhD thesis) — Related Work
[7] Constraint-programming-based code-generation approaches treat modulo scheduling as a set of additional constraints that interact with other code-generation subproblems (instruction selection, register/memory allocation) rather than as the core scheduling method, and CGRAs are mentioned as a target architecture class for such unified approaches. Arslan, Mehmet Ali (PhD thesis) — Related Work