Code Generation and Analysis for the Functional Verification of Microprocessors
PaperFirst seen 6/2/2026
Last seen 6/5/2026
Evidence 8 chunks
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20 connectionsThe paper introduces refdif as an architectural comparator tool.
The paper introduces SBVer as an external interface verifier tool.
The paper introduces the Profiler as a diagnostic analysis tool.
The paper introduces Theo as a sophisticated constraint-solving code generator.
The paper introduces MPApplicationVerifier for running real-world parallel applications as diagnostics.
The paper is authored by Anoosh Hosseini.
The paper is authored by Dimitrios Mavroidis.
The paper is authored by Pavlos Konas.
The paper introduces BRVer as a branch verifier tool.
The paper introduces MPVer for multiprocessor verification.
The paper introduces Ans as a diagnostic database query tool.
The paper introduces Streamer as an RTL trace conversion tool.
The paper uses run-time analysis to evaluate generated programs.
The paper mentions AVPGEN as a related test generator in the references.
The paper mentions MTPG as a related portable test generator for cache-coherent multiprocessors.
The paper presents tools employed in the simulation-based verification of microprocessor designs.
The paper addresses functional verification of microprocessors.
The paper focuses on code generation tools for microprocessor verification.
The paper evaluates functional coverage achieved by the code generation tools.
The paper is published by Silicon Graphics Inc.