Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

Paper

First seen 7/3/2026

Last seen 7/3/2026

Evidence 8 chunks

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RELATIONSHIPS

24 connections

e500 processor evaluates → 100% 3e

The paper applies its methodology on the e500 processor

Temporal Logic Properties uses → 100% 2e

The paper expresses desired behaviors as temporal logic properties

micro-architectural test generation introduces → 100% 2e

The paper presents a directed test generation technique at micro-architectural level

random test generation ← compares with 90% 2e

The paper contrasts directed test generation with random test generation

biased-random test generation ← compares with 90% 2e

The paper contrasts directed test generation with biased-random test generation

Property Decomposition uses → 95% 2e

The paper decomposes properties for efficient model checking

processor model decomposition uses → 95% 2e

The paper uses processor model decomposition to reduce search space

graph-based functional test program generation mentions → 85% 2e

The paper references graph-based functional test program generation as related work

model checker uses → 95% 2e

The paper uses a model checker as a test generation engine

decompositional model checking uses → 100% 2e

The paper uses decompositional model checking for systematic test generation

RTL Simulation uses → 95% 1e

The paper validates test cases via RTL simulation

Test Compaction mentions → 90% 1e

The paper mentions test compaction as future work

SAT-based bounded model checking mentions → 85% 1e

The paper references SAT-based bounded model checking in related work

Heon-Mo Koo authored by → 100% 1e

Heon-Mo Koo is listed as an author of the paper

dynamic speculation mentions → 85% 1e

The paper mentions dynamic speculation as a feature to extend the processor model for in future work

Prabhat Mishra authored by → 100% 1e

Prabhat Mishra is listed as an author of the paper

Jayanta Bhadra authored by → 100% 1e

Jayanta Bhadra is listed as an author of the paper

Magdy Abadir authored by → 100% 1e

Magdy Abadir is listed as an author of the paper

temporal specification language uses → 100% 1e

The processor model is described in a temporal specification language

Linear Temporal Logic (LTL) uses → 100% 1e

Properties are expressed in LTL

functional fault model uses → 95% 1e

Properties can be automatically generated from the input specification based on a functional fault model

pipeline graph coverage uses → 95% 1e

Properties can be automatically generated based on pipeline graph coverage

clock-based counterexample integration uses → 95% 1e

The paper proposes clock-based integration of partial counterexamples

Cadence SMV uses → 90% 1e

The paper references Cadence SMV as the model checking tool used