clock-based counterexample integration

Clock-based Counterexample Integration

Concept

Clock-based counterexample integration is a technique used in decompositional model checking of processor models to merge partial counterexamples generated from structurally decomposed modules into a coherent counterexample for the whole design, by aligning them along the model-checker's clock (clk) cycles.

First seen 7/3/2026

Last seen 7/3/2026

Evidence 1 chunks

Wiki v1

WIKI

Clock-based Counterexample Integration

Clock-based counterexample integration is a method used during the directed micro-architectural test generation of an industrial processor. It addresses a central challenge of decompositional model checking: after a processor model is split into structure-oriented modules (e.g., reservation stations, issue, decode, GIQ, rename buffer) and sub-properties are checked independently, the partial counterexamples produced for those modules must be combined into a single counterexample that is valid for the whole design.

Motivation

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study ← uses 95% 1e

The paper proposes clock-based integration of partial counterexamples

decompositional model checking ← uses 90% 1e

Decompositional model checking uses clock-based integration of partial counterexamples

LINKED ENTITIES

2 links

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study USES Extracted graph relationship

decompositional model checking USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Clock-based integration of partial counterexamples is proposed to address the challenge that relationships among decomposed modules and sub-properties are not preserved at the whole-design level. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[2] When two sub-properties are applied at the same clock cycle (clk = ts) to modules sharing a parent module, their counterexamples are merged into the output property of the parent module for generating counterexamples at the previous clock cycle (clk = ts − 1). Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[3] In the example, four reservation station (RS) modules share the parent module Issue, and counterexamples generated from multiple RS modules at cycle k are merged for creating the output property of the Issue stage, whose negated property is applied to the Issue module to generate a counterexample at cycle k − 1. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[4] The clock-based merging continues iteratively to derive output properties of Decode, GIQ, and Rename buffer, until a counterexample reaching the primary inputs is obtained. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[5] The clk variable counts time steps and ts is a specific time step used to align partial counterexamples during integration. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study

[6] The technique is presented as generic and applicable to validation of industrial-strength processors. Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study