RVDFI

Paper

First seen 6/5/2026

Last seen 6/5/2026

Evidence 15 chunks

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RELATIONSHIPS

37 connections

Dedicated DFI Cache introduces → 100% 2e

RVDFI introduces dedicated L0 caches for RDTable, RDSmap, and RDSet

Rocket Chip uses → 100% 2e

RVDFI leverages the open-source Rocket Chip SoC generator

RoCC uses → 100% 2e

RVDFI leverages RoCC as the dedicated DFI verification module

SPEC CPU2006 evaluates → 100% 2e

RVDFI evaluates performance using SPEC CPU2006 benchmark suite

HDFI ← compares with 95% 2e

RVDFI is compared with HDFI in terms of granularity and security

Static Analysis uses → 100% 2e

RVDFI uses static analysis to generate RDSets and instruction IDs

PIM-DFI ← compares with 95% 2e

RVDFI is compared with PIM-DFI in terms of performance overhead and hardware resources

Reaching Definition Set uses → 100% 2e

RVDFI uses reaching definition sets for DFI verification

Reaching Definition Table uses → 100% 2e

RVDFI uses a reaching definition table to record latest write instruction IDs

RDSmap uses → 100% 2e

RVDFI uses an RDSmap for indirect access to RDSets

Instruction Instrumentation uses → 100% 2e

RVDFI proposes a RISC-V architecture extension and instrumentation approach

custom0 instruction uses → 100% 2e

RVDFI uses the custom0 instruction to encode and transmit DFI information

Processor Pipeline uses → 90% 2e

RVDFI modifies the processor pipeline to pass DFI information

DFI Verification Flow introduces → 100% 2e

RVDFI introduces a DFI verification flow with offline and online parts

DFI Controller introduces → 100% 2e

RVDFI introduces a dedicated DFI controller inside RoCC

Near-Memory Processing mentions → 90% 2e

RVDFI mentions near-memory processing as used by PIM-DFI

RISC-V uses → 100% 2e

RVDFI is based on the RISC-V architecture

Dynamic Redundant Load Pruning introduces → 100% 2e

RVDFI introduces dynamic redundant load pruning to reduce performance overhead

Load Pruning Buffer introduces → 100% 2e

RVDFI introduces a load pruning buffer hardware design

Jump-Oriented Programming mentions → 90% 1e

RVDFI mentions jump-oriented programming as an attack detectable by DFI

Jiayi Huang authored by → 100% 1e

RVDFI paper is authored by Jiayi Huang

Luyi Li authored by → 100% 1e

RVDFI paper is authored by Luyi Li

Haochen Zhang authored by → 100% 1e

RVDFI paper is authored by Haochen Zhang

Zhongfeng Wang authored by → 100% 1e

RVDFI paper is authored by Zhongfeng Wang

LLVM uses → 100% 1e

RVDFI uses LLVM compiler infrastructure for static analysis

SVF uses → 100% 1e

RVDFI uses SVF framework for static value-flow analysis

Andersen's Algorithm uses → 100% 1e

RVDFI applies Andersen's algorithm for static analysis

DFI-Request FIFO introduces → 100% 1e

RVDFI introduces a DFI-Request FIFO to buffer requests and reduce stalling

Library Protection introduces → 100% 1e

RVDFI introduces library protection for dynamically linked functions

ISA Extension introduces → 100% 1e

RVDFI proposes a RISC-V ISA extension for DFI support

TMDFI compares with → 95% 1e

RVDFI is compared with TMDFI in terms of granularity and performance

Target Address Buffer uses → 100% 1e

RVDFI uses a target address buffer to pass target addresses along the pipeline

Miss Status Holding Registers uses → 90% 1e

RVDFI uses MSHRs to reduce performance overhead from cache misses

Control-Flow Integrity mentions → 90% 1e

RVDFI mentions control-flow integrity as a related security policy

Write Integrity Testing mentions → 90% 1e

RVDFI mentions write integrity testing as a partial DFI approach

Return-Oriented Programming mentions → 90% 1e

RVDFI mentions return-oriented programming as an attack detectable by DFI

Lang Feng authored by → 100% 1e

RVDFI paper is authored by Lang Feng