Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
PaperFirst seen 6/18/2026
Last seen 6/18/2026
Evidence 12 chunks
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20 connectionsThe paper evaluates the SPMIPS as an experimental case study.
The paper uses OBDDs to represent Boolean expressions in the implementation.
The paper references Burch's work on pipeline verification and superscalar processor verification.
The paper references Dill's work on pipeline verification.
The paper employs symbolic ternary simulation as its core verification technique.
The paper uses correspondence checking as one of the two forms of verification.
The paper extends and applies Burch and Dill's pipeline verification method.
The paper uses the EMM as memory model in its verification approach.
The paper uses STE as part of its four-step verification approach.
The paper makes memory shadowing applicable to symbolic ternary simulation.
The paper introduces ternary correspondence checking as a verification criterion.
The paper mentions transistor-level verification as the first step in the four-step approach.
Randal E. Bryant is listed as an author of the paper.
The paper is affiliated with Carnegie Mellon University.
The paper introduces the variable-group indexing technique.
The paper references Windley's work on proving correctness of the decomposition.
The paper references Pandey and Bryant's use of STE to verify memory arrays.
The paper discusses symbolic model checking as a related but complementary technique.
The paper mentions that circuit descriptions can be in gate-level or register-transfer-level form.
Miroslav N. Velev is listed as an author of the paper.