Randal E. Bryant — STIMSMITH

Randal E. Bryant

Person

Randal E. Bryant is an American computer scientist and academic associated with Carnegie Mellon University, known in the provided public context for research on formal verification of digital hardware and software. The provided technical evidence centers on a CMU report about verifying Y86-64 pipelined microprocessors with UCLID5, a formal-verification workflow involving Burch-Dill correspondence checking, automatically generated UCLID5 models from HCL control logic, and liveness checks to rule out pipeline deadlock.

First seen 5/25/2026

Last seen 6/5/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

Randal E. Bryant is an American computer scientist and academic noted for research on formal verification of digital hardware and software. Public context identifies him as a Carnegie Mellon University faculty member beginning in 1984, dean of Carnegie Mellon’s School of Computer Science from 2004 to 2014, and Founders University Professor Emeritus after retiring on June 30, 2020. [Bryant public biography]

Technical area represented in the evidence

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NEIGHBORHOOD

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RELATIONSHIPS

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Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic ← authored by 100% 2e

The paper is authored by Randal E. Bryant along with other authors.

LINKED ENTITIES

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Carnegie Mellon University affiliation Public context states that Bryant has been a faculty member at Carnegie Mellon University since 1984 and later became Founders University Professor Emeritus.

CITATIONS

11 sources

11 citations — click to expand

[1] Bryant public biography Randal Bryant

[2] Report title and verification setting Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] SEQ and PIPE equivalence task Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[4] Y86-64 ISA purpose Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[5] Y86-64 architectural state Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[6] UCLID5 modeling role Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[7] UCLID5 hardware modeling Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[8] Liveness requirement Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[9] HCL to UCLID5 generation Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[10] Common representation consistency Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[11] Experimental setup Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5