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Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

Paper
First seen 5/30/2026
Last seen 6/5/2026
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11 connections
Randal E. Bryant authored by → 100% 2e
The paper is authored by Randal E. Bryant along with other authors.
Propositional Logic uses → 100% 2e
The paper reduces EUF formulas to propositional formulas to enable Boolean verification methods.
Ordered Binary Decision Diagrams (BDDs) uses → 100% 2e
The paper applies BDDs as a Boolean method for processor verification after reducing EUF to propositional logic.
Burch-Dill Verification Method uses → 100% 2e
The paper presents experimental results using the Burch-Dill method for verifying pipelined processors.
Pipelined Processor Verification evaluates → 100% 2e
The paper presents experimental results on verifying pipelined processors.
Boolean Satisfiability Checking uses → 100% 2e
The paper applies Boolean satisfiability checkers as verification tools after reducing EUF to propositional logic.
Equality with Uninterpreted Functions (EUF) uses → 100% 2e
The paper uses EUF as a means of abstracting data manipulation by a processor during verification.
Control Logic Abstraction uses → 90% 1e
The paper uses EUF to abstract data manipulation when verifying processor control logic correctness.
Maximally Diverse Interpretations introduces → 95% 1e
The paper introduces the concept of maximally diverse interpretations to reduce the set of interpretations needed to prove universal validity.
Maximally Diverse Interpretations uses → 100% 1e
The paper exploits maximally diverse interpretations to simplify propositional formulas generated from EUF.
Processor Control Logic Verification evaluates → 100% 1e
The paper targets verification of processor control logic correctness using EUF reductions.