Burch-Dill Verification Method

Technique

A processor-verification technique referenced in the provided evidence as the method proposed by Burch and Dill for verifying pipelined processors. In the cited literature, it appears as the verification setting used to evaluate efficient reductions from equality with uninterpreted functions to propositional logic.

First seen 5/30/2026

Last seen 6/5/2026

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Burch-Dill Verification Method

Overview

The Burch-Dill Verification Method is identified in the provided evidence as a method proposed by Burch and Dill and used for verifying pipelined processors [C1].

Context in the provided evidence

The supplied source is a paper by Bryant et al. on reducing formulas in the logic of equality with uninterpreted functions (EUF) to propositional logic. That paper states that it presents experimental results demonstrating the efficiency of this approach when verifying pipelined processors using the method proposed by Burch and Dill [C2].

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RELATIONSHIPS

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Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic ← uses 100% 2e

The paper presents experimental results using the Burch-Dill method for verifying pipelined processors.

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Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic USES Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] The Burch-Dill Verification Method is described in the provided evidence as a method proposed by Burch and Dill for verifying pipelined processors. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

[2] Bryant et al. report experimental results demonstrating the efficiency of their EUF-to-propositional reduction approach when verifying pipelined processors using the method proposed by Burch and Dill. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

[3] The provided evidence does not supply additional procedural details of the Burch-Dill method beyond its use for verifying pipelined processors. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic