Boolean Satisfiability Checking

Technique

In the provided evidence, Boolean satisfiability checking is presented as a Boolean method that can be applied after reducing formulas in the logic of equality with uninterpreted functions (EUF) to propositional formulas. The cited paper uses this reduction-based approach for processor verification and reports efficient experimental results on pipelined processors.

First seen 5/30/2026

Last seen 6/5/2026

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Boolean Satisfiability Checking

Boolean satisfiability checking appears in the provided evidence as one of the Boolean methods used after reducing formulas in the logic of equality with uninterpreted functions (EUF) to propositional formulas. In this role, it is part of a verification workflow for processor control logic and is mentioned alongside Ordered Binary Decision Diagrams (BDDs). [C1]

Role in the cited verification approach

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Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic ← uses 100% 2e

The paper applies Boolean satisfiability checkers as verification tools after reducing EUF to propositional logic.

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CITATIONS

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3 citations — click to collapse

[1] Reducing EUF formulas to propositional formulas enables the use of Boolean satisfiability checkers, alongside BDDs, for verification. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

[2] The approach simplifies generated propositional formulas by exploiting verification-condition structure, including that many equations appear only in positive form, thereby restricting the interpretations that must be considered. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic

[3] The paper reports experimental results showing the efficiency of the approach for verifying pipelined processors using the Burch and Dill method. Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic