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Burch

Person

Burch is referenced in formal microprocessor verification for work with Dill in 1994 that introduced key ideas behind correspondence checking for pipelined processor designs, including automatic computation of an abstraction function by symbolic pipeline flushing.

First seen 5/25/2026
Last seen 6/5/2026
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Overview

Burch is cited together with Dill as the source of key ideas used in formal verification of pipelined microprocessors. The cited 1994 approach requires proving an abstraction function, α, that maps microprocessor states to architectural states and is maintained across each processor cycle. [C1]

Role in pipelined processor verification

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CITATIONS

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5 citations — click to expand
[1] C1: Burch and Dill's 1994 approach requires an abstraction function α mapping microprocessor states to architectural states and maintaining that mapping across processor cycles. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[2] C2: Formal pipelined microprocessor verification compares pipelined execution with a sequential ISA model whose architectural state includes registers, the program counter, and memory. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[3] C3: Burch and Dill's key contribution was automatic computation of the abstraction function by symbolic simulation during pipeline flushing, yielding the equivalence-checking approach called correspondence checking. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[4] C4: Burch and Dill demonstrated the value of data abstractions and term-level modeling in automated microprocessor verification, including symbolic terms and uninterpreted functions. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5
[5] C5: Burch-Dill verification proves safety but not liveness, because cycles may correspond to zero ISA steps and a deadlocked or inactive processor could still pass the safety verification. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5