Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

Paper

First seen 7/3/2026

Last seen 7/3/2026

Evidence 12 chunks

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RELATIONSHIPS

30 connections

FSM State Coverage uses → 100% 2e

The paper defines and uses FSM state coverage as a metric for test generation and compaction.

FSM Transition Coverage uses → 100% 2e

The paper defines and uses FSM transition coverage as a metric for test generation and compaction.

Unreachable State Identification uses → 95% 2e

The paper uses identification and removal of unreachable states as part of its FSM compaction technique.

Redundant State and Transition Elimination uses → 95% 2e

The paper eliminates redundant states and transitions to reduce test requirements.

Inevitable State uses → 90% 2e

The paper identifies inevitable states and transitions to eliminate redundant test cases.

Path Selection in FSM uses → 90% 2e

The paper uses FSM path selection to drive test generation covering maximum states and transitions.

MIPS Processor Model (FSM) evaluates → 100% 2e

The paper evaluates its test compaction methodology on a MIPS processor FSM model.

e500 Processor Model (FSM) evaluates → 100% 2e

The paper evaluates its test compaction methodology on an e500 processor FSM model.

Random Test Generation compares with → 90% 2e

The paper compares directed test generation to random test generation in terms of coverage efficiency.

Biased Random Test Generation compares with → 85% 2e

The paper compares directed tests to biased-random tests as current industrial practice.

Pipelined Processor Functional Validation uses → 100% 2e

The paper targets pipelined processor functional validation as its primary application domain.

Simulation-based Validation uses → 90% 2e

The paper discusses simulation-based validation as the context in which test compaction is applied.

FSM Coverage-Directed Test Generation introduces → 95% 2e

The paper introduces an FSM coverage-directed selection approach for test compaction and generation.

Test Compaction introduces → 100% 2e

The primary contribution of the paper is a test compaction technique for directed tests.

Finite State Machine (FSM) Model uses → 100% 2e

The paper creates an FSM model from processor specification to drive test generation and compaction.

Model Checking for Test Generation uses → 95% 2e

The paper uses model checking to generate test programs from selected FSM paths.

Pipeline Interaction Coverage uses → 90% 1e

FSM state coverage is equated to pipeline interaction coverage in the paper.

Counterexample-based Test Generation uses → 90% 1e

The paper exploits model checker counterexamples as test programs.

Illegal State Transition Identification uses → 90% 1e

The paper identifies illegal state transitions based on pipeline behavior rules.

Functional Fault uses → 90% 1e

The paper discusses functional faults as the target defects for directed test generation.

ISA-level Test Program Generation uses → 90% 1e

The paper generates test programs at the ISA level as part of its methodology.

Set Covering uses → 80% 1e

The paper references set covering as applied to static compaction procedures.

Architecture Description Language (ADL) uses → 90% 1e

The paper uses ADL specification to generate the FSM model of the processor.

Regression Testing mentions → 80% 1e

The paper mentions regression testing as a use case where test compaction has significant impact.

RTL Implementation uses → 85% 1e

The paper applies test compaction to reduce tests applied on the RTL implementation.

Fault Simulation uses → 75% 1e

The paper references fault simulation as used in dynamic test compaction techniques.

Heon-Mo Koo authored by → 100% 1e

Heon-Mo Koo is listed as an author of the paper.

Prabhat Mishra authored by → 100% 1e

Prabhat Mishra is listed as an author of the paper.

Genesys-Pro mentions → 85% 1e

The paper cites Genesys-Pro as a related tool for functional processor verification test generation.

Temporal Logic Property uses → 90% 1e

The paper uses temporal logic properties to express desired behaviors for model checking-based test generation.