Biased Random Test Generation

Technique

A test generation technique used in processor architecture verification in which random selections of test inputs are weighted toward values and conditions considered likely to activate design bugs. The approach was characteristic of many earlier architecture verification systems before constraint-based methods (such as AVPGEN's combination of symbolic execution and constraint solving) emerged as an alternative.

First seen 6/13/2026

Last seen 6/13/2026

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Biased Random Test Generation

Overview

Biased Random Test Generation is a test generation technique employed in hardware design verification, particularly for validating that processor implementations conform to their specified architectures. In contrast to purely uniform random generation, biased random generation uses biasing techniques—weighting functions that skew the probability distribution over test inputs—so that the generated tests more frequently exercise conditions judged "interesting" in that they are likely to activate various kinds of bugs in the design under test.

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NEIGHBORHOOD

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graph · Biased Random Test Generation · depth=1

RELATIONSHIPS

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Constraint-Based Initial Value Generation compares with → 85% 1e

AVPGEN's constraint-based approach is contrasted with earlier biased random test generation systems.

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Constraint-Based Initial Value Generation COMPARES_WITH Extracted graph relationship

CITATIONS

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3 citations — click to collapse

[1] Many earlier architecture verification test generation systems made biased random choices, in contrast to AVPGEN's approach of choosing intermediate or final values and solving for initial values. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)

[2] Biasing techniques (biasing functions) are used to focus generated tests on conditions that are interesting because they are likely to activate various kinds of bugs. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)

[3] AVPGEN combines user-specified constraints expressed in the SIGL (Symbolic Instruction Graph Language) template language with biasing functions to direct test generation toward bug-prone conditions. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)