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Biased Random Test Generation

Technique WIKI v1 · 6/13/2026

A test generation technique used in processor architecture verification in which random selections of test inputs are weighted toward values and conditions considered likely to activate design bugs. The approach was characteristic of many earlier architecture verification systems before constraint-based methods (such as AVPGEN's combination of symbolic execution and constraint solving) emerged as an alternative.

Biased Random Test Generation

Overview

Biased Random Test Generation is a test generation technique employed in hardware design verification, particularly for validating that processor implementations conform to their specified architectures. In contrast to purely uniform random generation, biased random generation uses biasing techniques—weighting functions that skew the probability distribution over test inputs—so that the generated tests more frequently exercise conditions judged "interesting" in that they are likely to activate various kinds of bugs in the design under test.

How the Technique Works

A test generator using biased random test generation selects intermediate or final architectural state values according to one or more biasing functions. These functions guide the random selection process so that corner cases, boundary conditions, and other bug-prone scenarios are explored more often than they would be under uniform random selection. The goal is to direct the limited test budget toward scenarios with higher expected defect density rather than wasting samples on conditions unlikely to reveal faults.

Relation to Constraint-Based Initial Value Generation

Biased Random Test Generation represents an earlier paradigm in automated test generation for architecture verification programs (AVPs). The AVPGEN system (IBM, published in IEEE Transactions on VLSI Systems, 1995) explicitly identifies this earlier paradigm as a foil for its own approach, observing that "many earlier systems make biased random choices" when selecting test values. AVPGEN instead combines symbolic execution and constraint solving—choosing intermediate or final values and then solving for the initial values that can lead to those desired states—rather than selecting initial values directly through biased random draws.

Even within AVPGEN's constraint-based framework, biasing functions are preserved as a complementary mechanism. AVPGEN's design provides the SIGL (Symbolic Instruction Graph Language) template language for users to express symbolic constraints, and the combination of user-specified constraints with biasing functions is used to focus generated tests on conditions likely to activate bugs. In this hybrid setting, biasing functions contribute to which target states are chosen, while constraint solving determines how the generator reaches those targets from valid initial states.

Industrial Use

The technique has been applied in industrial processor verification. While the AVPGEN paper documents the use of biasing-augmented constraint solving to debug many IBM S/390 processors as an integral part of the design process, biased random test generation as a standalone methodology was characteristic of the generation of test generation systems that preceded it.

See Also

LINKED ENTITIES

1 links
Constraint-Based Initial Value Generation COMPARES_WITH

CITATIONS

3 sources
3 citations
[1] Many earlier architecture verification test generation systems made biased random choices, in contrast to AVPGEN's approach of choosing intermediate or final values and solving for initial values. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)
[2] Biasing techniques (biasing functions) are used to focus generated tests on conditions that are interesting because they are likely to activate various kinds of bugs. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)
[3] AVPGEN combines user-specified constraints expressed in the SIGL (Symbolic Instruction Graph Language) template language with biasing functions to direct test generation toward bug-prone conditions. AVPGEN—A Test Generator for Architecture Verification, IEEE Transactions on VLSI Systems (IBM Research)