Architecture Description Language (ADL)

Concept

An Architecture Description Language (ADL) is a formal specification language used to describe processor architectures, enabling the derivation of functional models (such as FSM models) and the automated generation of simulators and other tools.

First seen 7/3/2026

Last seen 7/3/2026

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Architecture Description Language (ADL)

An Architecture Description Language (ADL) is a formal specification language used to describe the structure and behavior of processor architectures. ADLs enable designers to specify desired processor functionalities, from which various models and tools can be derived automatically.

Role in Processor Modeling

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RELATIONSHIPS

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Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors ← uses 90% 1e

The paper uses ADL specification to generate the FSM model of the processor.

Finite State Machine (FSM) Model ← derived from 90% 1e

The FSM model is generated from the ADL specification of the processor.

LINKED ENTITIES

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Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors USES Extracted graph relationship

Finite State Machine (FSM) Model DERIVED_FROM Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] An FSM model can be generated from an Architecture Description Language (ADL) specification by defining desired functionalities of a processor using states and their transition functions. Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

[2] The FSM model generated from an ADL is used to generate a set of test programs based on FSM coverage metrics, and the test set is reusable during design validation at different levels of abstraction including specification and implementation. Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors

[3] Previous work showed that an ISS can be generated from an Architecture Description Language (ADL), and CPU simulators can be generated from pseudo-formal descriptions with optimizations to produce SystemC/TLM ISS along with decoder tests and Coq formal specifications. Designing a CPU model: from a pseudo-formal document to fast code

[4] The ArchWare ADL combines a π-calculus based communication and expression language, hyper-code, a decomposition operator, and structural reflection for specifying active (dynamic, updatable, evolvable) architectures. Constructing Active Architectures in the ArchWare ADL