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Architecture Description Language (ADL)

Concept WIKI v1 · 7/3/2026

An Architecture Description Language (ADL) is a formal specification language used to describe processor architectures, enabling the derivation of functional models (such as FSM models) and the automated generation of simulators and other tools.

Architecture Description Language (ADL)

An Architecture Description Language (ADL) is a formal specification language used to describe the structure and behavior of processor architectures. ADLs enable designers to specify desired processor functionalities, from which various models and tools can be derived automatically.

Role in Processor Modeling

In the context of functional validation of pipelined processors, an FSM model can be generated from an ADL specification. The ADL specification is used to define desired functionalities of a processor using states and their transition functions. The resulting FSM model can then be used to generate test programs based on FSM coverage metrics, supporting design validation at different levels of abstraction including specification and implementation.

Related Languages and Approaches

The term "Architecture Description Language" has been applied to multiple distinct language families across different domains:

  • Processor ADLs — Used to specify processor architecture and generate functional models such as FSMs, as well as related tools like instruction-set simulators (ISSs).
  • Software ADLs (e.g., ArchWare ADL) — Used to specify active software architectures, combining concepts such as a π-calculus based communication and expression language for specifying executable architectures, hyper-code as an underlying representation of system execution, a decomposition operator to break up and introspect on executing systems, and structural reflection for creating new components and binding them into running systems.

Applications

ADLs have been used as a basis for:

  • Generating FSM models for functional validation and test generation
  • Generating full-system CPU simulators (ISS) from formal or pseudo-formal descriptions
  • Generating tests for decoders and formal specifications (e.g., in Coq)
  • Specifying dynamic, updatable, and evolvable software architectures

CITATIONS

4 sources
4 citations
[1] An FSM model can be generated from an Architecture Description Language (ADL) specification by defining desired functionalities of a processor using states and their transition functions. Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
[2] The FSM model generated from an ADL is used to generate a set of test programs based on FSM coverage metrics, and the test set is reusable during design validation at different levels of abstraction including specification and implementation. Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
[3] Previous work showed that an ISS can be generated from an Architecture Description Language (ADL), and CPU simulators can be generated from pseudo-formal descriptions with optimizations to produce SystemC/TLM ISS along with decoder tests and Coq formal specifications. Designing a CPU model: from a pseudo-formal document to fast code
[4] The ArchWare ADL combines a π-calculus based communication and expression language, hyper-code, a decomposition operator, and structural reflection for specifying active (dynamic, updatable, evolvable) architectures. Constructing Active Architectures in the ArchWare ADL