MIPS Processor Model (FSM)
ToolFirst seen 7/3/2026
Last seen 7/3/2026
Evidence 3 chunks
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2 connections Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors ← evaluates 100% 2e
The paper evaluates its test compaction methodology on a MIPS processor FSM model.
The MIPS processor model is implemented as an FSM for test generation purposes.