TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing
PaperFirst seen 7/12/2026
Last seen 7/12/2026
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22 connectionsThe paper introduces the Fuzzer Result Aggregation hardware unit as a new contribution.
The paper uses AFL++ as a baseline for performance comparison.
The paper uses QEMU-based AFL++ as a baseline comparison for ISA emulation fuzzing.
The paper introduces TaPaFuzz, the FPGA-accelerated RISC-V fuzzing framework.
The paper proposes hardware-based control flow tracing as the core monitoring technique.
The paper introduces the AXI Reset Wrapper as a novel hardware contribution.
The paper mentions AFL as the original fuzzer from which AFL++ and LibAFL derive.
The paper uses LibAFL as the base software fuzzer library.
The paper evaluates the CVA5 RISC-V core modified for fuzzing purposes.
The paper mentions LibFuzzer as a related fuzzing framework.
The paper mentions Michal Zalewski as the original developer of AFL.
The paper mentions Andrea Fioraldi as a main author of LibAFL.
The paper mentions Dominik Maier as a main author of LibAFL.
The TaPaFuzz paper cites the AFL++ paper as a reference.
Florian Meisel is listed as a co-author of the TaPaFuzz paper.
The TaPaFuzz paper cites the TaPaSCo toolflow paper.
David Volz is listed as a co-author of the TaPaFuzz paper.
Christoph Spang is listed as a co-author of the TaPaFuzz paper.
Dat Tran is listed as a co-author of the TaPaFuzz paper.
Andreas Koch is listed as a co-author of the TaPaFuzz paper.
The paper is produced by the Embedded Systems and Applications Group.
The paper is affiliated with Technical University of Darmstadt.