TaPaFuzz

Tool

First seen 7/12/2026

Last seen 7/12/2026

Evidence 10 chunks

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RELATIONSHIPS

33 connections

AFL ← compares with 100% 3e

TaPaFuzz is compared against AFL++ in terms of execution rate and coverage.

AXI Bus Protocol uses → 100% 3e

TaPaFuzz uses the AXI bus protocol for communication between PE components.

LibAFL uses → 100% 2e

TaPaFuzz uses LibAFL as its software fuzzer framework base.

TaPaSCo uses → 100% 2e

TaPaFuzz uses TaPaSCo as the FPGA abstraction framework for hardware/software integration.

CVA5 RISC-V Core uses → 100% 2e

TaPaFuzz uses the CVA5 RISC-V core as the processor inside the fuzzer PE.

AXI Reset Wrapper uses → 100% 2e

TaPaFuzz uses the AXI Reset Wrapper to handle partial design resets without hanging.

Fuzzer Result Aggregation Hardware uses → 100% 2e

TaPaFuzz uses the Fuzzer Result Aggregation hardware to collect control flow coverage.

Hardware-Based Control Flow Tracing implements → 100% 2e

TaPaFuzz implements hardware-based control flow tracing via the FRA hardware attached to the CVA5 core.

Control Flow Edge Coverage implements → 100% 2e

TaPaFuzz implements control flow edge coverage via its FRA hardware unit.

Fuzzer Result Aggregation implements → 100% 2e

TaPaFuzz implements fuzzer result aggregation in hardware for efficient coverage collection.

Partial Design Reset implements → 100% 2e

TaPaFuzz implements partial design reset support to reset the RISC-V core between fuzzer runs.

Cache Invalidation implements → 100% 2e

TaPaFuzz implements hardware-accelerated cache invalidation to maintain cache consistency between fuzzer runs.

Coverage Map uses → 100% 2e

TaPaFuzz uses a coverage map to record which CF edges have been observed.

Corpus uses → 100% 2e

TaPaFuzz uses a corpus of inputs that are mutated and executed in fuzzing iterations.

Input Mutation uses → 100% 2e

TaPaFuzz uses input mutation to generate new test inputs from existing corpus entries.

Interrupt Request uses → 100% 2e

TaPaFuzz uses an interrupt request signal to notify the host of finished target execution.

TaPaFuzz: An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing ← introduces 100% 2e

The paper introduces TaPaFuzz, the FPGA-accelerated RISC-V fuzzing framework.

FPGA Hardware Acceleration implements → 100% 2e

TaPaFuzz implements FPGA-based hardware acceleration for fuzzing.

processing element uses → 100% 2e

TaPaFuzz organizes its FPGA hardware as processing elements managed by TaPaSCo.

Scratchpad Memory uses → 90% 2e

TaPaFuzz uses scratchpad memory in the CVA5 core to reduce memory access latency.

ArduinoJson evaluates → 100% 2e

TaPaFuzz is evaluated by fuzzing the ArduinoJson library.

Soft-Core Processor uses → 100% 2e

TaPaFuzz uses a soft-core processor (CVA5) on the FPGA for executing fuzzing targets.

RISC-V ISA uses → 100% 2e

TaPaFuzz targets the RISC-V ISA for IoT fuzzing.

IoT Firmware uses → 100% 2e

TaPaFuzz targets IoT firmware for security vulnerability discovery.

Graybox Fuzzing implements → 100% 2e

TaPaFuzz implements graybox fuzzing by monitoring control flow on FPGA hardware.

PCIe Interface uses → 95% 2e

TaPaFuzz uses PCIe to transfer coverage maps from the FPGA to the host.

Memory-Mapped IO uses → 90% 1e

TaPaFuzz uses memory-mapped IO to pass arguments to the PE controller.

System On Chip uses → 85% 1e

TaPaFuzz uses TaPaSCo to compose SoCs consisting of heterogeneous processing elements onto FPGA.

Hash-Based Indexing implements → 100% 1e

TaPaFuzz implements hash-based indexing for coverage map entries in the FRA hardware.

fuzz testing implements → 100% 1e

TaPaFuzz implements fuzz testing for RISC-V IoT devices.

DDR4 Memory uses → 90% 1e

TaPaFuzz optionally uses DDR4 memory as an alternative to BRAM for larger targets.

Xilinx Vivado uses → 90% 1e

TaPaFuzz is implemented and synthesized using Xilinx Vivado.

libtapasco uses → 100% 1e

TaPaFuzz uses libtapasco runtime library to interact with FPGA hardware.