Cache Invalidation

Concept

Cache invalidation is the process of removing or marking cached data entries as invalid so that stale state cannot be reused. It is employed in two principal domains discussed in the evidence: (1) hardware processor caches, where on-chip caches must be synchronized with newly uploaded program or data memory contents (as implemented by TaPaFuzz on the CVA5 RISC-V core), and (2) software/algorithmic caches (e.g., LRU caches of critic evaluations in MetaDOAR) where invalidated entries must be evicted to preserve decision quality. In shared-memory cache coherence, invalidation traffic is a known scalability bottleneck, motivating protocols such as Tardis that aim to remove or reduce invalidation messages.

First seen 7/12/2026

Last seen 7/12/2026

Evidence 2 chunks

Wiki v1

WIKI

Definition

Cache invalidation is the operation of discarding or marking as invalid entries held in a cache so that subsequent reads cannot observe stale data. The need for invalidation arises whenever the authoritative source of a cached value changes (or, in hardware, whenever the contents of backing memory have been replaced wholesale, as when a new program is loaded into a processor's instruction memory).

Hardware Cache Invalidation

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RELATIONSHIPS

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TaPaFuzz ← implements 100% 2e

TaPaFuzz implements hardware-accelerated cache invalidation to maintain cache consistency between fuzzer runs.

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TaPaFuzz IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] Cache invalidation is requested for the data cache during job preparation on a Fuzzer PE that uses caches to accelerate DRAM access. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[2] On initial instruction memory upload, additional invalidations for the instruction cache and branch predictor caches are issued. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[3] In the CVA5 RISC-V core, tag memories for instruction and data caches, as well as the branch predictor, persist through a reset, motivating explicit invalidation after program memory upload. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[4] TaPaFuzz implements dedicated hardware support for accelerated cache invalidations that invalidate tags at the rate of one set per clock cycle, independent of cache associativity. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[5] Cache coherence scalability is a major challenge in shared memory systems because traditional protocols do not scale due to the storage and traffic overhead of cache invalidation. Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models

[6] The Tardis coherence protocol removes cache invalidation by using logical timestamps to achieve scalability, with Tardis 2.0 extending the approach to TSO, PSO, and Release Consistency. Tardis 2.0: Optimized Time Traveling Coherence for Relaxed Consistency Models

[7] MetaDOAR caches batched critic evaluations in an LRU cache keyed by quantized state projection and local action identifiers, and uses conservative k-hop cache invalidation to evict entries within k hops of a modified region. A Scalable Approach to Solving Simulation-Based Network Security Games