AXI Bus Protocol

Concept

The AXI (Advanced eXtensible Interface) bus protocol is an on-chip communication standard used in the TaPaFuzz FPGA-accelerated graybox fuzzing framework, where a RISC-V CVA5 processor accesses instruction, data, and result memories over AXI4 slave and master ports. An AXI Reset Wrapper shim is placed between the CVA5 core and the downstream AXI4 memory bus to complete in-flight transactions when the core is reset, preventing the bus from locking up.

First seen 7/12/2026

Last seen 7/12/2026

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AXI Bus Protocol

Overview

The AXI (Advanced eXtensible Interface) bus protocol is a point-to-point on-chip interconnect standard used to connect processing elements to memory and control resources. In the TaPaFuzz framework, AXI is used to wire the CVA5 RISC-V core to the BRAM-based instruction, data, and result memories, as well as to provide PE control and optional DRAM access.

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TaPaFuzz ← uses 100% 3e

TaPaFuzz uses the AXI bus protocol for communication between PE components.

AXI Reset Wrapper ← implements 100% 2e

The AXI Reset Wrapper implements AXI protocol compliance during partial design resets.

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AXI Reset Wrapper IMPLEMENTS Extracted graph relationship

CITATIONS

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[1] The Fuzzer PE in TaPaFuzz has two AXI slave ports (S_AXI_CTRL for control/reset/restart and S_AXI_BRAM for writing instruction, data, and fuzzing-result memories) plus an optional AXI master port for connecting to an AXI-DRAM controller. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[2] A wrapper module is placed in-between the CVA5 core and the downstream AXI4 memory bus to complete remaining transactions even when the core resets, while passing AXI signals combinationally and keeping a registered copy of each handshake from the core during normal operation. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[3] The AXI Reset Wrapper maintains counters for in-flight requests and the remaining number of beats in a write transaction, and stalls write handshakes only if the burst-length FIFO or an in-flight access counter would overflow; for the CVA5, this stalling does not occur in practice because the core sends all write beats before starting the next burst. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[4] On a synchronous local core reset, the AXI Reset Wrapper stabilizes pending handshake requests using registered copies until accepted by the bus, sends write beats with all bytes disabled (wstrb set to 0) for each outstanding write burst, and waits for all response handshakes (final read beats and write responses) before notifying the fuzzing controller that the bus is stable and the reset can be released. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing

[5] The AXI Reset Wrapper shim is portable across different cores or other AXI components, making only two assumptions beyond the AXI standard: the core never issues write-beat (data) handshakes before the write-burst request (address, length), and no more than a configurable number of in-flight read requests (default 15) are sent by the core and accepted by the downstream bus. TaPaFuzz - An FPGA-Accelerated Framework for RISC-V IoT Graybox Fuzzing