Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V
PaperFirst seen 7/3/2026
Last seen 7/3/2026
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19 connectionsThe paper employs data propagation analysis to ensure test signatures are meaningful.
The paper introduces RISCV-ISAC as a coverage measurement and data propagation analysis tool.
Neel Gala is listed as an author of the paper.
Allen Baum is listed as an author of the paper.
The paper is published under InCore Semiconductors copyright.
The paper discusses architectural testing as its core topic.
The paper targets RISC-V as the ISA of interest.
The paper discusses the relationship between architectural testing and design verification.
The paper compares RISCV-CTG with mutation-based test generation.
The paper's approach mandates signature-based tests.
The paper proposes an ISA coverage specification format to measure test quality.
The paper references the RISC-V Test Format Specification for standardized test macros.
The paper uses coverpoints expressed in Python to define coverage requirements.
The paper presents directed test generation as the approach for creating efficient tests.
The paper models coverpoints as constraint satisfaction problems to generate test solutions.
The paper compares its approach with SMT solver-based test generation by Herdt et al.
S Pawan Kumar is listed as an author of the paper.
The paper discusses negative testing and why it is not feasible for architectural testing.
Shrreya Singh is listed as an author of the paper.