Architectural Testing
ConceptArchitectural (Compatibility) Testing verifies that an ISA implementation satisfies all architectural requirements under all conditions. For RISC-V, which is micro-architecture agnostic and extremely configurable, an exhaustive test suite is impractical, so architectural testing focuses on a limited subset of the ISA. Architectural testing is a subset of design verification, not a replacement for it: it only checks details specified in the ISA and does not ensure full functional correctness of an implementation.
First seen 7/3/2026
Last seen 7/3/2026
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Architectural Testing
Definition
Architectural (Compatibility) Testing (AT) ensures that an implementation of an ISA meets all the requirements specified by the architecture under all conditions. For RISC-V, which is micro-architecture agnostic and extremely configurable, it is impossible to create an exhaustive test suite covering all implementations; instead, a suite is built that targets limited areas of the ISA [8bde013b].
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3 connections Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V ← mentions 100% 1e
The paper discusses architectural testing as its core topic.
Architectural testing is described as a subset of design verification.
Architectural testing in the paper is specifically for RISC-V.
CITATIONS
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[1] Architectural (Compatibility) Testing ensures that an implementation of the ISA meets all the requirements under all conditions. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[2] RISC-V is micro-architecture agnostic and extremely configurable, so an exhaustive test suite for all implementations is impossible; instead, a suite that tests limited areas of the ISA can be built. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[3] AT is a subset of design verification and is not sufficient by itself to ensure a functionally correct implementation; it only deals with verification of details specified in the ISA. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[4] The RISC-V Architectural Test SIG has released a Test Format Specification that provides standard macros, keeping tests immune to implementation-specific choices and behaviour; it mandates signature-based tests compared against a golden model. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[5] Challenges include standardised test format, an ISA coverage specification format, a tool to measure coverage, and a tool to generate efficient directed tests. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[6] Contributions of the toolchain include low barriers to entry (simple ISA coverage specification, simulator-independent, basic Python required), directed tests generated from coverpoints, data propagation analysis ensuring signatures are influenced by tests, and open-source tools for coverage and test generation. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[7] A coverpoint specifies a boolean expression over the fields of an architectural element (instruction or state) that is required to be covered during execution. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[8] In classical DV, coverpoints are defined in SV-UVM for the RTL with a high entry barrier (expensive, requires SystemVerilog knowledge) and it is extremely difficult to implement all possible architectural options in a single RTL; in ISAC, coverpoints are expressed as pure Python expressions. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[9] Coverpoints are categorised by Instruction Mnemonics (Opcode), Register Operands, Operand Combinations, Value Combinations, CSR Value Combinations, and Cross Combinations; custom Python functions (abstract_comb) are resolved into standard coverpoints during normalization. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022
[10] Coverage is computed from an instruction trace containing the instruction address, instruction encoding, and architectural state changes (CSR and regfile updates); the trace parser and decoder are implemented as plugins, architectural states are maintained internally, instructions influencing coverage can be filtered, coverage collection can be constrained to specific covergroups, and custom signature-region boundaries can be specified. Automating Generation and Maintenance of a High-Quality Architectural Test Suite for RISC-V - CARRV at ISCA 2022