Directed Test Generation

Concept

Directed test generation is a RISC-V verification technique that uses targeted stimulus and structured test suites to exercise specific ISA features, compliance points, and coverage gaps. Evidence indicates that it is most effective when combined with constrained-random generation: random tests explore broad state spaces, while directed tests provide precision for features such as privilege behavior, virtual memory, PMP/ePMP, vector extensions, and compliance-focused architectural validation.

First seen 5/26/2026

Last seen 5/29/2026

Evidence 5 chunks

Wiki v1

WIKI

Directed Test Generation

Overview

Directed test generation is the use of intentionally targeted stimulus to exercise specific design features, architectural behaviors, or known coverage gaps. In RISC-V processor verification, directed tests are used alongside constrained-random tests because each approach covers different verification needs: random stimulus explores broad and unexpected state spaces, while directed tests provide structure and precision for requirements that random generation may not fully exercise. [C1]

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Hybrid Verification Methodology ← uses 98% 2e

The hybrid methodology combines directed suites with constrained-random stimulus to achieve coverage closure.

ImperasTS ← implements 97% 2e

ImperasTS provides directed test suites targeting specific RISC-V features for structured verification.

LINKED ENTITIES

4 links

STING supports_directed_test_generation The evidence states that STING generates constrained-random and directed tests, produces ASM-style directed tests, includes a framework for directed-test development, and uses stimulus graphs to schedule random and directed tests.

ImperasDV supports_reference_model_comparison The evidence states that ImperasDV enables lock-step comparison against a reference model at instruction retirement.

ImperasFC supports_coverage_analysis The evidence states that ImperasFC generates SystemVerilog coverage models from the ISA specification and is used for functional coverage analysis in the hybrid flow.

ImperasSC enables_pre_rtl_stimulus_coverage The evidence states that coverage analysis can begin before RTL using ImperasSC, enabling shift-left verification.

CITATIONS

11 sources

11 citations — click to expand

[1] Directed tests provide structure and precision, while constrained-random tests explore broad and unexpected state spaces; the recommended approach combines both. source

[2] In the described RISC-V flow, STING is used for discovery and ImperasTS directed suites are used for targeted closure. source

[3] Random stimulus can leave gaps in features such as privilege-mode transitions, page-table walks, and memory protection. source

[4] STING generates C++-based random streams and ASM-style directed tests, includes a framework for directed-test development, and uses stimulus graphs to schedule random and directed tests. source

[5] STING-generated programs are portable across simulation, emulation, FPGA prototypes, and silicon, and are architecturally self-checking. source

[6] ImperasTS includes TS-ISA architectural validation tests, TS-VECT vector-extension tests, and TS-MMU/PMP/ePMP directed suites for virtual memory and protection features. source

[7] ImperasTS directed suites target areas where random stimulus often leaves gaps; TS-MMU tests are described as exposing a TLB flush ordering issue after weak Sv39/Sv48 page-table-walk coverage was found. source

[8] A typical hybrid workflow begins with STING constrained-random sweeps, then uses ImperasFC functional coverage analysis and directed tests to close highlighted gaps. source

[9] ImperasSC enables pre-RTL coverage analysis and shift-left verification; coverage results can be merged in Verdi and failing cases replayed deterministically in VCS. source

[10] Generated tests can run in VCS with Verdi debug, use ImperasDV lock-step reference-model comparison at instruction retirement, and be reused in ZeBu emulation or HAPS prototyping. source

[11] A hybrid directed and random approach is described as improving coverage closure, debug efficiency, scalability, reproducibility, portability, and support for RISC-V privilege and extension features. source