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Directed Test Generation

Concept WIKI v1 · 5/26/2026

Directed test generation is a RISC-V verification technique that uses targeted stimulus and structured test suites to exercise specific ISA features, compliance points, and coverage gaps. Evidence indicates that it is most effective when combined with constrained-random generation: random tests explore broad state spaces, while directed tests provide precision for features such as privilege behavior, virtual memory, PMP/ePMP, vector extensions, and compliance-focused architectural validation.

Directed Test Generation

Overview

Directed test generation is the use of intentionally targeted stimulus to exercise specific design features, architectural behaviors, or known coverage gaps. In RISC-V processor verification, directed tests are used alongside constrained-random tests because each approach covers different verification needs: random stimulus explores broad and unexpected state spaces, while directed tests provide structure and precision for requirements that random generation may not fully exercise. [C1]

The evidence describes directed generation as part of a hybrid verification strategy: constrained-random stimulus is used for discovery, and directed suites are used for targeted closure and compliance-oriented validation. [C2]

Why directed tests are needed

Random testing is effective for uncovering unanticipated behavior, but random stimulus alone can leave important architectural areas insufficiently exercised. Examples called out in the evidence include privilege-mode transitions, page-table walks, and memory protection. [C3]

Directed tests address this by systematically targeting such features. However, directed suites also have a limitation: because they are structured around known scenarios, they may miss subtle unexpected interactions. The recommended strategy is therefore not directed-only testing, but a combined flow in which random testing discovers unexpected behavior and directed tests close specific coverage or compliance gaps. [C1]

Directed generation with STING

STING is described as a RISC-V bare-metal functional verification tool that supports both constrained-random and directed stimulus. It produces C++-based random streams and ASM-style directed tests, and includes a programming framework for developing directed tests. It also uses stimulus graphs to control scheduling of both random and directed tests. [C4]

The generated programs are portable across simulation, emulation, FPGA prototypes, and silicon, and are architecturally self-checking. This portability supports reuse of directed and random stimulus across multiple verification stages. [C5]

Directed suites with ImperasTS

ImperasTS is presented as a family of directed RISC-V test suites used to address gaps found during coverage analysis. The evidence identifies several suite categories:

  • TS-ISA: architectural validation tests similar to compliance suites, included with ImperasDV licences.
  • TS-VECT: targeted suites for vector extensions.
  • TS-MMU / PMP / ePMP: directed suites for virtual memory and protection features. [C6]

These suites are configured to match the user’s RISC-V processor and are used where random stimulus often leaves gaps. The evidence gives an example in which coverage analysis found weak points in Sv39 and Sv48 page-table walks; adding TS-MMU tests exposed an ordering issue in TLB flush logic. [C7]

Role in coverage closure

Directed test generation is used as part of an iterative coverage-closure flow. A typical workflow begins with constrained-random sweeps using STING, followed by functional coverage analysis using ImperasFC, which generates SystemVerilog coverage models from the ISA specification. Coverage gaps are then highlighted and closed with directed stimulus or directed suites. [C8]

Coverage analysis can also begin before RTL using ImperasSC, enabling a shift-left verification approach. Once RTL is available, coverage results can be merged in Verdi, and failing cases can be replayed deterministically in VCS. [C9]

Integration with reference models and execution platforms

Directed tests are most effective when integrated with simulation, debug, reference-model comparison, and hardware-assisted validation platforms. The evidence states that generated programs can run in simulators such as VCS, with Verdi used for centralized debug. ImperasDV provides lock-step comparison against a reference model at instruction retirement, helping catch errors early. The same stimulus can also be reused in ZeBu emulation or HAPS prototyping, extending validation to system-level workloads. [C10]

Benefits

A hybrid approach that includes directed test generation provides several reported benefits:

  • Faster coverage closure by combining random exploration with precise directed tests.
  • Improved debug efficiency through self-checking tests and lock-step comparison.
  • Scalability from embedded cores to multi-hart systems.
  • Reproducibility through logged seeds and directed reruns.
  • Portability across simulation, emulation, FPGA prototyping, and silicon.
  • Support for verification of RISC-V profiles and privilege-related features such as MMU, PMP, hypervisor, and vector extensions. [C11]

Practical use pattern

A practical directed-generation workflow is:

  1. Start with broad constrained-random stimulus to find unexpected behavior.
  2. Analyze functional and stimulus coverage.
  3. Identify uncovered or weakly covered architectural features.
  4. Add directed tests or targeted directed suites for those gaps.
  5. Run with reference-model comparison and debug tooling.
  6. Replay failures deterministically and iterate until coverage closure is achieved. [C8] [C9] [C10]

LINKED ENTITIES

4 links
STING supports_directed_test_generation
ImperasDV supports_reference_model_comparison
ImperasFC supports_coverage_analysis
ImperasSC enables_pre_rtl_stimulus_coverage

CITATIONS

11 sources
11 citations
[1] Directed tests provide structure and precision, while constrained-random tests explore broad and unexpected state spaces; the recommended approach combines both. source
[2] In the described RISC-V flow, STING is used for discovery and ImperasTS directed suites are used for targeted closure. source
[3] Random stimulus can leave gaps in features such as privilege-mode transitions, page-table walks, and memory protection. source
[4] STING generates C++-based random streams and ASM-style directed tests, includes a framework for directed-test development, and uses stimulus graphs to schedule random and directed tests. source
[5] STING-generated programs are portable across simulation, emulation, FPGA prototypes, and silicon, and are architecturally self-checking. source
[6] ImperasTS includes TS-ISA architectural validation tests, TS-VECT vector-extension tests, and TS-MMU/PMP/ePMP directed suites for virtual memory and protection features. source
[7] ImperasTS directed suites target areas where random stimulus often leaves gaps; TS-MMU tests are described as exposing a TLB flush ordering issue after weak Sv39/Sv48 page-table-walk coverage was found. source
[8] A typical hybrid workflow begins with STING constrained-random sweeps, then uses ImperasFC functional coverage analysis and directed tests to close highlighted gaps. source
[9] ImperasSC enables pre-RTL coverage analysis and shift-left verification; coverage results can be merged in Verdi and failing cases replayed deterministically in VCS. source
[10] Generated tests can run in VCS with Verdi debug, use ImperasDV lock-step reference-model comparison at instruction retirement, and be reused in ZeBu emulation or HAPS prototyping. source
[11] A hybrid directed and random approach is described as improving coverage closure, debug efficiency, scalability, reproducibility, portability, and support for RISC-V privilege and extension features. source