ImperasTS
ToolImperasTS is a family of directed RISC-V verification test suites used to close coverage gaps in architectural, vector, virtual-memory, and protection-feature validation. The evidence identifies TS-ISA, TS-VECT, and TS-MMU/PMP/ePMP suites, describes them as self-checking and reference-model-compared, and places them in a hybrid verification flow with constrained-random STING stimulus, ImperasFC/SC coverage, ImperasDV lock-step comparison, VCS simulation, and Verdi debug.
First seen 5/26/2026
Last seen 5/26/2026
Evidence 3 chunks
Wiki v1
WIKI
Overview
ImperasTS is described as a set of directed test suites for RISC-V processor verification. In the cited verification flow, ImperasTS complements constrained-random stimulus by providing structured, targeted tests for areas where random generation may leave coverage gaps. [C1]
Test-suite family
NEIGHBORHOOD
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8 connectionsImperasTS provides directed test suites targeting specific RISC-V features for structured verification.
ImperasTS-ISA is a member of the ImperasTS family providing architectural validation tests.
ImperasTS-VECT is a member of the ImperasTS family providing targeted suites for vector extensions.
ImperasTS-MMU is a member of the ImperasTS family providing directed suites for virtual memory.
ImperasTS-PMP is a member of the ImperasTS family providing directed suites for memory protection.
ImperasTS-ePMP is a member of the ImperasTS family providing directed suites for enhanced memory protection.
VCS executes ImperasTS directed suites as part of the verification flow.
The hybrid methodology uses ImperasTS directed suites for structured compliance and feature coverage.
LINKED ENTITIES
6 linksImperasDV included_with_or_integrates_with The evidence states that TS-ISA is included with ImperasDV licences and that ImperasDV enables lock-step comparison against a reference model.
STING complements The evidence describes a hybrid methodology where constrained-random STING stimulus uncovers unexpected behavior while ImperasTS directed suites provide structured closure.
ImperasFC used_with_for_coverage_analysis The evidence describes a flow that uses constrained-random sweeps followed by functional coverage analysis with ImperasFC, then targeted closure using directed suites.
ImperasSC used_with_for_shift_left_coverage The evidence states that coverage analysis can begin before RTL using ImperasSC, enabling a shift-left verification approach.
VCS executes_directed_suites The evidence describes VCS as executing STING-generated random tests and ImperasTS directed suites, and also mentions deterministic replay of failing cases in VCS.
Verdi used_with_for_debug_and_coverage_reporting The evidence identifies Verdi as a debug and analysis platform used for waveforms, mismatch tracking, and functional coverage reporting, and describes coverage results being merged or viewed in Verdi.
CITATIONS
15 sources15 citations — click to expand
[1] C1: ImperasTS is used as a directed-suite component that complements constrained-random stimulus for RISC-V verification and coverage closure. source
[2] C2: The ImperasTS family includes TS-ISA architectural validation tests, TS-VECT vector-extension tests, and TS-MMU/PMP/ePMP suites for virtual-memory and protection features. source
[3] C3: The vector, MMU, PMP, and ePMP test suites are configured to match the user's RISC-V processor. source
[4] C4: The described hybrid flow starts with constrained-random sweeps, uses ImperasFC functional coverage analysis, and closes gaps with targeted directed tests. source
[5] C5: A cited example says TS-MMU tests exposed a subtle TLB-flush ordering issue after coverage analysis revealed weak Sv39 and Sv48 page-table-walk coverage. source
[6] C6: ImperasTS suites are self-checking and automatically compare results against a reference model, helping uncover subtle design issues and accelerate coverage closure. source
[7] C7: Lock-step comparison runs RTL and a golden reference model in parallel and compares results at instruction retirement for early bug detection. source
[8] C8: STING provides constrained-random and directed RISC-V stimulus, while ImperasTS directed suites are used for compliance and feature coverage in the same methodology. source
[9] C9: ImperasFC generates SystemVerilog functional coverage models from the ISA specification, and coverage results can be viewed or merged in Verdi. source
[11] C11: VCS is described as executing STING-generated random tests and ImperasTS directed suites, and failing cases can be replayed deterministically in VCS. source
[12] C12: The evidence claims faster coverage closure from combining STING random stimulus with precise ImperasTS directed tests. source
[13] C13: The evidence claims improved debug efficiency from combining architecturally self-checking tests with ImperasDV lock-step comparison. source
[14] C14: The evidence says tests are portable across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon, supporting shift-left methodology. source
[15] C15: The evidence states that the flow supports RISC-V profiles RVA22 and RVA23 and covers privilege-related areas including MMU, PMP, hypervisor, and vector extensions. source