Skip to content
STIMSMITH

ImperasTS

Tool WIKI v1 · 5/26/2026

ImperasTS is a family of directed RISC-V verification test suites used to close coverage gaps in architectural, vector, virtual-memory, and protection-feature validation. The evidence identifies TS-ISA, TS-VECT, and TS-MMU/PMP/ePMP suites, describes them as self-checking and reference-model-compared, and places them in a hybrid verification flow with constrained-random STING stimulus, ImperasFC/SC coverage, ImperasDV lock-step comparison, VCS simulation, and Verdi debug.

Overview

ImperasTS is described as a set of directed test suites for RISC-V processor verification. In the cited verification flow, ImperasTS complements constrained-random stimulus by providing structured, targeted tests for areas where random generation may leave coverage gaps. [C1]

Test-suite family

The ImperasTS family identified in the evidence includes:

  • TS-ISA: architectural validation tests, similar to compliance suites, included with ImperasDV licences. [C2]
  • TS-VECT: targeted suites for RISC-V vector extensions. [C2]
  • TS-MMU / PMP / ePMP: directed suites for virtual-memory and memory-protection features. [C2]

The evidence states that the vector, MMU, PMP, and ePMP suites are configured to match the user's RISC-V processor. [C3]

Verification role

ImperasTS is positioned as the directed-test component in a hybrid RISC-V verification methodology. The flow begins with broader constrained-random sweeps, then uses coverage analysis to identify weak areas, and applies directed ImperasTS suites to close remaining gaps. [C4]

A reported example describes coverage analysis finding weak points in Sv39 and Sv48 page-table walks; adding TS-MMU tests then exposed a subtle ordering issue in TLB flush logic. [C5]

Checking and debug

ImperasTS suites are described as self-checking and as automatically comparing results against a reference model. This makes them useful for exposing subtle design issues while accelerating coverage closure. [C6]

In a broader debug flow, architecturally self-checking tests can be combined with ImperasDV lock-step comparison, where RTL and a golden reference model are compared at instruction retirement to identify mismatches early. [C7]

Flow integration

The evidence places ImperasTS alongside several other verification tools:

  • STING supplies constrained-random and directed bare-metal stimulus; ImperasTS supplies directed suites for structured closure. [C8]
  • ImperasFC can generate SystemVerilog functional coverage models from the ISA specification, with results viewable in coverage tools such as Verdi. [C9]
  • ImperasSC enables coverage analysis before RTL, supporting shift-left verification. [C10]
  • VCS is described as executing STING-generated random tests and ImperasTS directed suites. [C11]
  • Verdi is used for coverage reporting, waveform/debug analysis, and mismatch tracking in the described environment. [C9]

Benefits described in the evidence

The cited material attributes several verification benefits to using ImperasTS as part of a hybrid RISC-V flow:

  • Faster coverage closure, because random stimulus explores unexpected behavior while ImperasTS suites provide precise directed tests. [C12]
  • Improved debug efficiency when self-checking tests are combined with ImperasDV lock-step comparison. [C13]
  • Portability and shift-left enablement when stimulus and coverage methods are reused across simulation, emulation, prototyping, and silicon-oriented validation stages. [C14]
  • Future-ready compliance coverage for RISC-V profiles and privilege-related areas such as MMU, PMP, hypervisor, and vector extensions. [C15]

See also

LINKED ENTITIES

6 links
ImperasDV included_with_or_integrates_with
STING complements
ImperasFC used_with_for_coverage_analysis
ImperasSC used_with_for_shift_left_coverage
VCS executes_directed_suites
Verdi used_with_for_debug_and_coverage_reporting

CITATIONS

15 sources
15 citations
[1] C1: ImperasTS is used as a directed-suite component that complements constrained-random stimulus for RISC-V verification and coverage closure. source
[2] C2: The ImperasTS family includes TS-ISA architectural validation tests, TS-VECT vector-extension tests, and TS-MMU/PMP/ePMP suites for virtual-memory and protection features. source
[3] C3: The vector, MMU, PMP, and ePMP test suites are configured to match the user's RISC-V processor. source
[4] C4: The described hybrid flow starts with constrained-random sweeps, uses ImperasFC functional coverage analysis, and closes gaps with targeted directed tests. source
[5] C5: A cited example says TS-MMU tests exposed a subtle TLB-flush ordering issue after coverage analysis revealed weak Sv39 and Sv48 page-table-walk coverage. source
[6] C6: ImperasTS suites are self-checking and automatically compare results against a reference model, helping uncover subtle design issues and accelerate coverage closure. source
[7] C7: Lock-step comparison runs RTL and a golden reference model in parallel and compares results at instruction retirement for early bug detection. source
[8] C8: STING provides constrained-random and directed RISC-V stimulus, while ImperasTS directed suites are used for compliance and feature coverage in the same methodology. source
[9] C9: ImperasFC generates SystemVerilog functional coverage models from the ISA specification, and coverage results can be viewed or merged in Verdi. source
[10] C10: ImperasSC enables pre-RTL coverage analysis and supports shift-left verification. source
[11] C11: VCS is described as executing STING-generated random tests and ImperasTS directed suites, and failing cases can be replayed deterministically in VCS. source
[12] C12: The evidence claims faster coverage closure from combining STING random stimulus with precise ImperasTS directed tests. source
[13] C13: The evidence claims improved debug efficiency from combining architecturally self-checking tests with ImperasDV lock-step comparison. source
[14] C14: The evidence says tests are portable across simulation, ZeBu emulation, HAPS FPGA prototyping, and silicon, supporting shift-left methodology. source
[15] C15: The evidence states that the flow supports RISC-V profiles RVA22 and RVA23 and covers privilege-related areas including MMU, PMP, hypervisor, and vector extensions. source