ImperasTS-MMU

Tool

ImperasTS-MMU is a directed RISC-V test suite in the ImperasTS family for virtual-memory verification. The evidence describes it as part of the TS-MMU/PMP/ePMP group of directed suites for virtual memory and protection features, used to target coverage gaps that random stimulus may miss, including Sv39 and Sv48 page-table-walk scenarios and TLB flush ordering behavior.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

ImperasTS-MMU is part of the ImperasTS family of RISC-V verification test suites. In the available evidence, it is grouped with ImperasTS-PMP and ImperasTS-ePMP as a set of directed suites for virtual memory and protection features.^[1]

Verification role

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

ImperasTS part of → 99% 1e

ImperasTS-MMU is a member of the ImperasTS family providing directed suites for virtual memory.

MMU evaluates → 99% 1e

ImperasTS-MMU provides directed suites for virtual memory and MMU verification.

Page Table Walk evaluates → 94% 1e

ImperasTS-MMU tests exposed a subtle ordering issue in TLB flush logic after revealing weak points in page table walks.

TLB Flush Logic evaluates → 95% 1e

Adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic.

Sv39 evaluates → 93% 1e

Coverage analysis revealed weak points in Sv39 page table walks, leading to use of TS-MMU tests.

Sv48 evaluates → 93% 1e

Coverage analysis revealed weak points in Sv48 page table walks, leading to use of TS-MMU tests.

LINKED ENTITIES

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Page Table Walk TARGETS Extracted graph relationship

Sv39 TARGETS Extracted graph relationship

Sv48 TARGETS Extracted graph relationship

TLB Flush Logic EXPOSES Extracted graph relationship

CITATIONS

5 sources

5 citations — click to expand

[1] ImperasTS-MMU is part of the ImperasTS family and is grouped with PMP and ePMP directed suites for virtual memory and protection features. source

[2] ImperasTS directed suites efficiently target areas where random stimulus often leaves gaps. source

[3] After coverage analysis revealed weak points in Sv39 and Sv48 page table walks, adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic. source

[4] The test suites for vector, MMU, PMP, and ePMP are configured to match the user's RISC-V processor. source

[5] A hybrid verification flow combines constrained-random sweeps, functional coverage analysis, and targeted directed tests for coverage closure. source