MMU

Concept

The Memory Management Unit (MMU) is a hardware feature that translates virtual addresses to physical addresses and enforces memory protection. In RISC-V contexts, it supports virtual memory schemes such as Sv39 and Sv48 with multi-level page tables, and it is a critical verification target in commercial cores and processor verification flows. The ultraembedded/riscv core provides optional, basic MMU support sufficient for booting Linux with SW-emulated atomics, while verification methodologies combine constrained-random and directed test suites to cover page-table walks and TLB behavior.

First seen 5/26/2026

Last seen 8/3/2026

Evidence 5 chunks

Wiki v2

WIKI

Overview

A Memory Management Unit (MMU) is a hardware component that translates virtual addresses to physical addresses and enforces memory-access protection. The provided evidence discusses the MMU in three contexts:

As a verification target for RISC-V processors, where directed suites target virtual-memory and protection behavior.^[1]^[2]
As an optional hardware block in the open-source ultraembedded/riscv core, where basic MMU support enables booting Linux (using SW-emulated atomics for the A extension).^[3]
As a security/comparison reference against alternative isolation mechanisms (e.g., CHERI capability isolation, MPUs) in embedded systems without an MMU.^[4]
As the conceptual basis for the PIM-MMU architecture, which applies MMU-style address translation and scheduling to processing-in-memory systems.^[5]

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NEIGHBORHOOD

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RELATIONSHIPS

7 connections

Sv48 ← part of 92% 2e

Sv48 is a RISC-V virtual memory scheme using 48-bit virtual addresses, part of the MMU specification.

RISC-V ISA part of → 92% 2e

The MMU is part of the RISC-V ISA for virtual memory management.

Sv39 ← part of 92% 2e

Sv39 is a RISC-V virtual memory scheme using 39-bit virtual addresses, part of the MMU specification.

Page Table Walk ← part of 91% 2e

Page table walks are a core mechanism within the MMU for address translation.

RISC-V CPU Core (ultraembedded/riscv) ← implements 97% 1e

The core includes basic MMU support capable of booting Linux.

TLB Flush Logic ← part of 90% 1e

TLB flush logic is a component of the MMU responsible for invalidating TLB entries.

ImperasTS-MMU ← evaluates 99% 1e

ImperasTS-MMU provides directed suites for virtual memory and MMU verification.

LINKED ENTITIES

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RISC-V CPU Core (ultraembedded/riscv) IMPLEMENTS Extracted graph relationship

CITATIONS

14 sources

14 citations — click to expand

[1] MMU is a critical RISC-V privilege-related verification area in hybrid verification flows. RISC-V Test Generation: Random, Directed, and Coverage

[2] Random testing alone may leave gaps in page-table-walk and memory-protection behavior. RISC-V Test Generation: Random, Directed, and Coverage

[3] Hybrid constrained-random and directed testing is recommended for RISC-V verification. RISC-V Test Generation: Random, Directed, and Coverage

[4] ImperasTS includes TS-MMU / PMP / ePMP directed suites for virtual memory and protection features. RISC-V Test Generation: Random, Directed, and Coverage

[5] Sv39 and Sv48 are RISC-V virtual memory schemes with 39-bit and 48-bit virtual addresses and multi-level page tables. RISC-V Test Generation: Random, Directed, and Coverage

[6] TS-MMU tests exposed a subtle ordering issue in TLB flush logic after Sv39/Sv48 page-table-walk coverage analysis. RISC-V Test Generation: Random, Directed, and Coverage

[7] STING constrained-random stimulus exposed deadlocks in page-table walks. RISC-V Test Generation: Random, Directed, and Coverage

[8] Coverage closure flow combines STING, ImperasFC, Verdi, and VCS for iterative MMU verification. RISC-V Test Generation: Random, Directed, and Coverage

[9] Targeted ImperasTS suites are recommended for compliance, MMU, PMP, and vector extension coverage gaps. RISC-V Test Generation: Random, Directed, and Coverage

[10] STING is effective at stressing privilege levels, memory protection, CSRs, and hypervisor extensions. RISC-V Test Generation: Random, Directed, and Coverage

[11] PMP and ePMP restrict memory-region access for privilege, isolation, and security policies. RISC-V Test Generation: Random, Directed, and Coverage

[12] The ultraembedded/riscv core is a 32-bit RISC-V Verilog CPU with optional basic MMU support (SUPPORT_MMU) sufficient to boot Linux using SW-emulated RV-A atomics. ultraembedded/riscv

[13] MMU-less Linux lacks protection/isolation mechanisms and CHERI is proposed to provide MMU-like spatial memory safety by isolating user programs as separate ELFs with distinct capability tables and isolating the kernel. Case Study: Securing MMU-less Linux Using CHERI

[14] PIM-MMU is a hardware/software codesign for energy-efficient DRAM-to/from-PIM data transfers combining a hardware data copy engine, a PIM-optimized memory scheduler, and a heterogeneity-aware memory mapping function, achieving 4.1× throughput and energy-efficiency gains and 2.2× end-to-end speedup. PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems