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MMU

Concept

The Memory Management Unit (MMU) is a hardware component that translates virtual addresses to physical addresses and enforces memory-access protection. Evidence discusses the MMU in RISC-V as a verification target alongside features like PMP and hypervisor support, as an optional block in the ultraembedded/riscv core, as a baseline for isolation guarantees compared with CHERI on MMU-less embedded Linux, and as the conceptual basis for the PIM-MMU processing-in-memory architecture. Verification flows combine constrained-random stimulus (STING) with directed suites (ImperasTS TS-MMU) to close coverage gaps in Sv39/Sv48 page-table walks and TLB flush logic, and graph-based CSP techniques have been used in industrial microprocessor MMU verification.

First seen 5/26/2026
Last seen 9/24/2026
Evidence 6 chunks
Wiki v3

WIKI

Overview

A Memory Management Unit (MMU) is a hardware component that translates virtual addresses to physical addresses and enforces memory-access protection. The provided evidence discusses the MMU in several contexts:

  1. As a hardware address-translation mechanism in modern microprocessors whose verification has been addressed using graph-based constraint satisfaction (GCSP) techniques.[1]
  2. As a critical RISC-V privilege-related verification target alongside PMP, ePMP, hypervisor, and vector features, addressed via hybrid constrained-random + directed flows.[2][3]
  3. As an optional hardware block in the open-source ultraembedded/riscv core, where basic MMU support enables booting Linux (using SW-emulated atomics for the A extension).[4]
  4. As a security/comparison reference against alternative isolation mechanisms (e.g., CHERI capability isolation, MPUs) in embedded systems without an MMU.[5]
  5. As the conceptual basis for the PIM-MMU architecture, which applies MMU-style address translation and scheduling to processing-in-memory systems.[6]
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NEIGHBORHOOD

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RELATIONSHIPS

8 connections
Page Table Walk ← part of 91% 2e
Page table walks are a core mechanism within the MMU for address translation.
RISC-V ISA part of → 92% 2e
The MMU is part of the RISC-V ISA for virtual memory management.
Sv39 ← part of 92% 2e
Sv39 is a RISC-V virtual memory scheme using 39-bit virtual addresses, part of the MMU specification.
Sv48 ← part of 92% 2e
Sv48 is a RISC-V virtual memory scheme using 48-bit virtual addresses, part of the MMU specification.
MMU verification ← evaluates 98% 1e
The verification activity targets memory management units (MMUs).
TLB Flush Logic ← part of 90% 1e
TLB flush logic is a component of the MMU responsible for invalidating TLB entries.
RISC-V CPU Core (ultraembedded/riscv) ← implements 97% 1e
The core includes basic MMU support capable of booting Linux.
ImperasTS-MMU ← evaluates 99% 1e
ImperasTS-MMU provides directed suites for virtual memory and MMU verification.

LINKED ENTITIES

4 links
MMU verification EVALUATES Extracted graph relationship
CHERI ALTERNATIVE_TO CHERI is proposed in the cited case study as an alternative isolation mechanism providing MMU-like protection on MMU-less Linux.
Sv39 IMPLEMENTED_BY Sv39 is described as a RISC-V virtual-memory scheme that defines the page-table structure traversed by the MMU.
Sv48 IMPLEMENTED_BY Sv48 is described as a RISC-V virtual-memory scheme with 48-bit virtual addresses that defines the page-table structure traversed by the MMU.

CITATIONS

13 sources
13 citations — click to expand
[1] The MMU is a hardware component that translates virtual addresses to physical addresses and enforces memory-access protection. Using Graph-Based CSP to Solve the Address Translation Problem for CP 2016 - IBM Research
[2] Modern microprocessor MMU address translation can be modeled as a directed acyclic graph and verified with graph-based constraint satisfaction problems (GCSP), an algorithm based on conditional CSP used to verify the MMUs of several industrial microprocessors. Using Graph-Based CSP to Solve the Address Translation Problem for CP 2016 - IBM Research
[3] The ultraembedded/riscv core is a 32-bit RISC-V Verilog CPU supporting RV32IMZicsr with optional basic MMU support that can boot Linux with SW-emulated RV-A atomics, configurable via SUPPORT_MMU. ultraembedded/riscv
[4] MMU is a critical RISC-V privilege-related verification area covered alongside PMP, ePMP, hypervisor, and vector extensions in a hybrid constrained-random plus directed flow. RISC-V test generation: random, directed, coverage
[5] ImperasTS includes TS-MMU / PMP / ePMP directed suites for virtual memory and protection features, configurable to match the user's RISC-V processor. RISC-V test generation: random, directed, coverage
[6] Random stimuli alone may not fully exercise page-table walks and memory-protection features, motivating hybrid constrained-random and directed testing for MMU verification. RISC-V test generation: random, directed, coverage
[7] Sv39 and Sv48 are RISC-V virtual-memory schemes that define multi-level page table structures for address translation. RISC-V test generation: random, directed, coverage
[8] After coverage analysis revealed weak points in Sv39 and Sv48 page-table walks, adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic. RISC-V test generation: random, directed, coverage
[9] STING has exposed issues such as deadlocks in page-table walks. RISC-V test generation: random, directed, coverage
[10] A coverage-closure flow starts with STING constrained-random sweeps, applies functional coverage analysis with ImperasFC, merges results in Verdi, and replays failing cases in VCS. RISC-V test generation: random, directed, coverage
[11] Targeted ImperasTS suites are recommended for compliance, MMU, PMP, and vector extensions where coverage gaps remain. RISC-V test generation: random, directed, coverage
[12] MMU-less Linux lacks protection/isolation, and CHERI is proposed to provide MMU-like spatial memory safety by isolating user programs as separate ELFs and isolating the kernel via separate capability tables. Case Study: Securing MMU-less Linux Using CHERI
[13] PIM-MMU is a hardware/software codesign providing energy-efficient DRAM-to/from-PIM transfers via a data copy engine, PIM-optimized memory scheduler, and heterogeneity-aware memory mapping, achieving 4.1x average throughput/energy-efficiency improvement and 2.2x end-to-end speedup. PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems