MMU

Concept

In the provided RISC-V verification evidence, MMU is discussed as a virtual-memory-management feature area that requires targeted verification. Random stimulus may leave gaps in page-table-walk behavior, while directed TS-MMU suites are used to exercise virtual memory scenarios such as Sv39 and Sv48 page-table walks and to expose issues such as TLB flush ordering problems.

First seen 5/26/2026

Last seen 5/26/2026

Evidence 4 chunks

Wiki v1

WIKI

Overview

In this evidence set, MMU is treated as a RISC-V virtual-memory-management verification target. It appears alongside PMP, ePMP, hypervisor, and vector features as one of the critical privilege-related areas that verification flows should cover.^[1]

MMU-related behavior is called out as difficult to cover with random testing alone. The evidence notes that features such as privilege-mode transitions, page table walks, and memory protection may not be fully exercised by random generation.^[2]

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NEIGHBORHOOD

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RELATIONSHIPS

6 connections

RISC-V ISA part of → 92% 2e

The MMU is part of the RISC-V ISA for virtual memory management.

Sv39 ← part of 92% 2e

Sv39 is a RISC-V virtual memory scheme using 39-bit virtual addresses, part of the MMU specification.

Sv48 ← part of 92% 2e

Sv48 is a RISC-V virtual memory scheme using 48-bit virtual addresses, part of the MMU specification.

Page Table Walk ← part of 91% 2e

Page table walks are a core mechanism within the MMU for address translation.

ImperasTS-MMU ← evaluates 99% 1e

ImperasTS-MMU provides directed suites for virtual memory and MMU verification.

TLB Flush Logic ← part of 90% 1e

TLB flush logic is a component of the MMU responsible for invalidating TLB entries.

LINKED ENTITIES

10 links

RISC-V verification_context The evidence discusses MMU in the context of RISC-V processor verification and RISC-V privilege specifications.

ImperasTS provides_directed_tests_for The evidence states that ImperasTS includes directed suites, including TS-MMU / PMP / ePMP, for virtual memory and protection features.

Sv39 virtual_memory_scheme_relevant_to The evidence defines Sv39 as a RISC-V virtual memory scheme and discusses Sv39 page table walks in MMU testing.

Sv48 virtual_memory_scheme_relevant_to The evidence defines Sv48 as a RISC-V virtual memory scheme and discusses Sv48 page table walks in MMU testing.

STING generates_stimulus_for The evidence says STING generates constrained-random and directed RISC-V tests and has exposed issues such as deadlocks in page-table walks.

PMP co_verified_feature The evidence groups MMU with PMP in directed suites and verification recommendations.

ePMP co_verified_feature The evidence groups MMU with ePMP in directed suites for virtual memory and protection features.

ImperasFC supports_coverage_analysis_for The evidence describes a workflow using ImperasFC functional coverage analysis after constrained-random sweeps to identify coverage gaps.

VCS replays_failing_cases_for The evidence says failing cases are replayed deterministically in VCS as part of the coverage-closure loop.

Verdi reports_coverage_for The evidence says coverage results are merged and viewed in Verdi.

CITATIONS

11 sources

11 citations — click to expand

[1] MMU is a critical RISC-V privilege-related verification area. source

[2] Random testing may miss page table walks and related privilege or protection behavior. source

[3] Hybrid constrained-random and directed testing is recommended for RISC-V verification. source

[4] ImperasTS includes TS-MMU / PMP / ePMP directed suites for virtual memory and protection features. source

[5] Sv39 and Sv48 define multi-level RISC-V virtual-memory page-table structures. source

[6] TS-MMU tests exposed a TLB flush ordering issue after Sv39/Sv48 page-table-walk coverage gaps were found. source

[7] STING exposed deadlocks in page-table walks. source

[8] Coverage closure flow uses STING, ImperasFC, Verdi, and VCS. source

[9] Targeted ImperasTS suites are recommended for MMU coverage gaps. source

[10] STING stresses privilege and memory-protection-related RISC-V areas. source

[11] PMP and ePMP restrict memory-region access for privilege, isolation, and security policies. source