Sv48
ConceptSv48 is a RISC-V virtual memory scheme that uses 48-bit virtual addresses and defines a multi-level page-table structure for address translation. In RISC-V verification, Sv48 page-table walks are a directed-test target, including through ImperasTS-MMU suites for virtual-memory features.
First seen 5/25/2026
Last seen 5/26/2026
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Overview
Sv48 is a RISC-V virtual memory scheme. Alongside Sv39, it is identified as one of the RISC-V virtual-memory modes used for address translation; Sv48 specifically uses 48-bit virtual addresses. These schemes define multi-level page-table structures for translating virtual addresses. [Sv48 definition]
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2 connectionsSv48 is a RISC-V virtual memory scheme using 48-bit virtual addresses, part of the MMU specification.
Coverage analysis revealed weak points in Sv48 page table walks, leading to use of TS-MMU tests.