Overview

Sv48 is a RISC-V virtual memory scheme. Alongside Sv39, it is identified as one of the RISC-V virtual-memory modes used for address translation; Sv48 specifically uses 48-bit virtual addresses. These schemes define multi-level page-table structures for translating virtual addresses. [Sv48 definition]

Verification relevance

Sv48 is relevant to RISC-V processor verification because its page-table walks can contain coverage-sensitive behavior. Evidence from a RISC-V verification flow describes coverage analysis finding weak points in Sv39 and Sv48 page-table walks; adding ImperasTS-MMU tests then exposed a subtle ordering issue in TLB flush logic. [Sv48 page-table-walk verification]

Directed testing

The ImperasTS family includes ImperasTS-MMU / PMP / ePMP, described as directed suites for virtual-memory and protection features. These directed suites are used to target areas where random stimulus may leave verification gaps, and the suites can be configured to match the user's RISC-V processor. [ImperasTS-MMU targeting]

Related entity

• ImperasTS-MMU — directed test-suite technology that targets virtual-memory behavior, including Sv48 page-table-walk scenarios. [ImperasTS-MMU targeting]