Sv39

Concept

Sv39 is a RISC-V virtual memory scheme that uses 39-bit virtual addresses and defines a multi-level page table structure for address translation. In RISC-V verification, Sv39 page table walks can be specifically targeted by directed MMU test suites such as ImperasTS-MMU to close coverage gaps and expose translation-related implementation issues.

First seen 5/25/2026

Last seen 5/26/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Sv39 is a RISC-V virtual memory scheme. It uses 39-bit virtual addresses and defines a multi-level page table structure for address translation.

Sv39 is discussed alongside Sv48, another RISC-V virtual memory scheme that uses 48-bit virtual addresses. Both schemes are relevant to verification activities involving page table walks and address translation behavior.

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RELATIONSHIPS

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MMU part of → 92% 2e

Sv39 is a RISC-V virtual memory scheme using 39-bit virtual addresses, part of the MMU specification.

ImperasTS-MMU ← evaluates 93% 1e

Coverage analysis revealed weak points in Sv39 page table walks, leading to use of TS-MMU tests.

LINKED ENTITIES

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ImperasTS-MMU TARGETS Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] Sv39 is a RISC-V virtual memory scheme that uses 39-bit virtual addresses and defines a multi-level page table structure for address translation. source

[2] Sv39 is discussed alongside Sv48, which uses 48-bit virtual addresses, as part of RISC-V virtual memory schemes. source

[3] ImperasTS-MMU is a directed suite for virtual memory and protection features. source

[4] Coverage analysis found weak points in Sv39 and Sv48 page table walks, and adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic. source