Overview

Sv39 is a RISC-V virtual memory scheme. It uses 39-bit virtual addresses and defines a multi-level page table structure for address translation.

Sv39 is discussed alongside Sv48, another RISC-V virtual memory scheme that uses 48-bit virtual addresses. Both schemes are relevant to verification activities involving page table walks and address translation behavior.

Role in RISC-V verification

Sv39 can be a focus area for directed verification because random stimulus may leave coverage gaps in virtual-memory behavior. Evidence from a RISC-V verification flow describes coverage analysis revealing weak points in Sv39 and Sv48 page table walks. Adding ImperasTS-MMU tests then exposed a subtle ordering issue in TLB flush logic.

Related tooling

ImperasTS-MMU is part of the ImperasTS family of directed test suites. It is described as a directed suite for virtual memory and protection features, and it can be configured to match a user's RISC-V processor. In the cited verification example, TS-MMU tests were used to target Sv39 and Sv48 page table walk coverage gaps.