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STIMSMITH

ImperasTS-MMU

Tool WIKI v1 · 5/25/2026

ImperasTS-MMU is a directed RISC-V test suite in the ImperasTS family for virtual-memory verification. The evidence describes it as part of the TS-MMU/PMP/ePMP group of directed suites for virtual memory and protection features, used to target coverage gaps that random stimulus may miss, including Sv39 and Sv48 page-table-walk scenarios and TLB flush ordering behavior.

Overview

ImperasTS-MMU is part of the ImperasTS family of RISC-V verification test suites. In the available evidence, it is grouped with ImperasTS-PMP and ImperasTS-ePMP as a set of directed suites for virtual memory and protection features.[1]

Verification role

ImperasTS-MMU is described as a directed test suite intended to target areas where random stimulus often leaves coverage gaps.[2] This positions it as a complement to constrained-random verification flows: random testing can expose broad behavior, while directed TS-MMU tests can be added to close specific virtual-memory coverage holes.

Targeted MMU scenarios

The evidence gives a specific example in which coverage analysis found weak points in Sv39 and Sv48 page table walks. Adding TS-MMU tests then exposed a subtle ordering issue in TLB flush logic.[3]

This supports the following technical characterization:

  • Sv39 targeting: TS-MMU can be applied to coverage gaps involving Sv39 page table walks.[3]
  • Sv48 targeting: TS-MMU can be applied to coverage gaps involving Sv48 page table walks.[3]
  • Page-table-walk focus: The example explicitly identifies page table walks as a weak area that TS-MMU tests helped address.[3]
  • TLB flush exposure: The example reports that TS-MMU tests exposed an ordering issue in TLB flush logic.[3]

Configuration

The test suites for vector, MMU, PMP, and ePMP are described as configurable to match the user's RISC-V processor.[4]

Use in a hybrid verification flow

The evidence describes a hybrid coverage-closure flow in which constrained-random sweeps are followed by functional coverage analysis, after which directed tests such as TS-MMU can be used to target weak spots.[5] In this role, ImperasTS-MMU contributes targeted closure for virtual-memory behavior rather than replacing random stimulus.

[1]: ImperasTS-MMU/PMP/ePMP are listed as directed suites for virtual memory and protection features in evidence chunk b73d6860-3caf-4eb7-811e-eda1693f60f3. [2]: The evidence states that these directed suites efficiently target areas where random stimulus often leaves gaps in chunk b73d6860-3caf-4eb7-811e-eda1693f60f3. [3]: The evidence states that weak points in Sv39 and Sv48 page table walks were addressed by adding TS-MMU tests, which exposed a subtle ordering issue in TLB flush logic, in chunk b73d6860-3caf-4eb7-811e-eda1693f60f3. [4]: The evidence states that the test suites for vector, MMU, PMP, and ePMP are configured to match the user's RISC-V processor in chunk b73d6860-3caf-4eb7-811e-eda1693f60f3. [5]: The evidence describes a hybrid flow combining constrained-random sweeps, functional coverage analysis, and directed test closure in chunk b73d6860-3caf-4eb7-811e-eda1693f60f3.

LINKED ENTITIES

4 links
Page Table Walk TARGETS
Sv39 TARGETS
Sv48 TARGETS
TLB Flush Logic EXPOSES

CITATIONS

5 sources
5 citations
[1] ImperasTS-MMU is part of the ImperasTS family and is grouped with PMP and ePMP directed suites for virtual memory and protection features. source
[2] ImperasTS directed suites efficiently target areas where random stimulus often leaves gaps. source
[3] After coverage analysis revealed weak points in Sv39 and Sv48 page table walks, adding TS-MMU tests exposed a subtle ordering issue in TLB flush logic. source
[4] The test suites for vector, MMU, PMP, and ePMP are configured to match the user's RISC-V processor. source
[5] A hybrid verification flow combines constrained-random sweeps, functional coverage analysis, and targeted directed tests for coverage closure. source