Capability Mode Bit

Concept

A capability mode bit is an architectural feature supported in CHERI (Capability Hardware Enhanced RISC Instructions) implementations for RISC-V. The Piccolo and Flute microcontroller extensions were the first CHERI implementations to support a merged register file combined with a capability mode bit.

First seen 6/8/2026

Last seen 6/8/2026

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Capability Mode Bit

Overview

A capability mode bit is an architectural feature used in CHERI (Capability Hardware Enhanced RISC Instructions) implementations. It allows a processor to switch between addressing and execution modes in which capabilities are interpreted, enabling the integration of capability-aware logic into general-purpose RISC-V pipelines.

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UCAM-CL-TR-984 ← uses 100% 2e

The thesis implements and evaluates the capability mode bit for CHERI microcontrollers.

CHERI ← uses 100% 2e

CHERI uses a capability mode bit to switch between capability and legacy modes.

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CITATIONS

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[1] The Piccolo and Flute microcontroller extensions were the first CHERI implementations to support a merged register file and capability mode bit. UCAM-CL-TR-984: Efficient spatial and temporal safety for microcontrollers and application-class processors

[2] The thesis explored microarchitectural implications of a dynamically switched capability encoding mode as an architectural improvement for CHERI RISC-V. UCAM-CL-TR-984: Efficient spatial and temporal safety for microcontrollers and application-class processors