Capability Mode Bit

Overview

A capability mode bit is an architectural feature used in CHERI (Capability Hardware Enhanced RISC Instructions) implementations. It allows a processor to switch between addressing and execution modes in which capabilities are interpreted, enabling the integration of capability-aware logic into general-purpose RISC-V pipelines.

First Implementations

The capability mode bit was first introduced into CHERI implementations as part of extensions to the Piccolo and Flute microcontrollers. According to UCAM-CL-TR-984, these microcontroller extensions were "the first CHERI implementations supporting a merged register file and capability mode bit". This combination of a merged register file with the capability mode bit presented new microarchitectural tradeoffs for the RISC-V adaptation of CHERI.

Dynamically Switched Capability Encoding Mode

The thesis (UCAM-CL-TR-984) further explored the microarchitectural implications of a "dynamically switched capability encoding mode" as one of the architectural improvements investigated for CHERI RISC-V. This line of work examines how the capability mode bit can be exploited to change capability encodings at runtime, offering flexibility in how capability metadata is represented and processed.

Context within CHERI Research

The capability mode bit sits alongside other CHERI microarchitectural features explored in the same body of work, including:

The merged capability register file
Tag clearing instead of exceptions on monotonicity violations
The Sentry (Secure Entry) mechanism

These features were investigated in the context of extending CHERI from its original MIPS implementation to RISC-V microcontrollers and, ultimately, to an open superscalar out-of-order application-class core (RiscyOO, based on Toooba).