Piccolo (RISC-V implementation)
ToolPiccolo is a simple 32-bit RISC-V implementation discussed in the TestRIG work. In that context, Piccolo is an RVFI-DII-instrumented target whose simple single-issue design allowed direct replacement of the instruction cache with a DII queue delivering one compressed or uncompressed instruction per cycle.
First seen 5/30/2026
Last seen 6/8/2026
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WIKI
Overview
Piccolo is identified in the TestRIG paper as a simple 32-bit RISC-V implementation, listed alongside RVBS, Ibex, Flute, and Toooba as implementations used in the randomized-testing ecosystem. The paper states that these implementations are written in either SystemVerilog or Bluespec.
Role in TestRIG
NEIGHBORHOOD
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10 connectionsTestRIG is used to validate correctness of the Piccolo CHERI implementation.
Piccolo is a simple 32-bit in-order pipeline processor.
The thesis evaluates the CHERI-extended Piccolo microcontroller including area, frequency, performance, and power overheads.
Piccolo is extended with CHERI modifications providing CHERI capability support.
Piccolo is a RISC-V microcontroller from Bluespec.
Piccolo is a microcontroller-class processor from Bluespec.
Piccolo as a RISC-V microcontroller supports Physical Memory Protection.
Piccolo is implemented in Bluespec HDL.
Piccolo is one of the first CHERI implementations to support a merged register file.
Piccolo has been instrumented with RVFI-DII.
CITATIONS
4 sources4 citations — click to collapse
[1] Piccolo is listed as a simple 32-bit RISC-V implementation in the TestRIG ecosystem, among implementations written in either SystemVerilog or Bluespec. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG participants require an RVFI-DII interface, an 8 MiB memory region at 0x80000000, access faults for other addresses, and reset to a known state on a reset DII packet. Randomized Testing of RISC-V CPUs using Direct
[3] RVFI-DII combines Direct Instruction Injection for instruction input with RVFI for trace output, supporting interactive verification. Randomized Testing of RISC-V CPUs using Direct
[4] Piccolo's simple single-issue design allowed the instruction cache to be replaced with a DII queue delivering one compressed or uncompressed instruction every cycle. Randomized Testing of RISC-V CPUs using Direct