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Piccolo (RISC-V implementation)

Tool WIKI v1 · 5/30/2026

Piccolo is a simple 32-bit RISC-V implementation discussed in the TestRIG work. In that context, Piccolo is an RVFI-DII-instrumented target whose simple single-issue design allowed direct replacement of the instruction cache with a DII queue delivering one compressed or uncompressed instruction per cycle.

Overview

Piccolo is identified in the TestRIG paper as a simple 32-bit RISC-V implementation, listed alongside RVBS, Ibex, Flute, and Toooba as implementations used in the randomized-testing ecosystem. The paper states that these implementations are written in either SystemVerilog or Bluespec.

Role in TestRIG

TestRIG is a randomized testing ecosystem for RISC-V CPUs that standardizes communication between verification engines, models, and implementations. To participate, an implementation must be extended with RVFI-DII instrumentation. TestRIG participants are expected to be architecturally identical and to provide an 8 MiB memory region at 0x80000000, with other addresses returning access faults, and to reset to a known state when a reset DII packet is injected.

RVFI-DII integration

RVFI-DII combines RVFI trace output with Direct Instruction Injection input. RVFI exposes architecturally significant trace information such as instruction encoding, memory address/value information, and operand/writeback register indices and values. DII supplies instructions to the implementation, while RVFI reports the resulting trace, enabling interactive verification.

For Piccolo, the paper highlights that its simple single-issue design made RVFI-DII integration comparatively direct: Piccolo and Flute could replace the instruction cache entirely with a DII queue that delivered one instruction every cycle, either compressed or uncompressed. This contrasts with more complex superscalar designs, where instruction picking and cancellation required additional synchronization mechanisms.

Key technical characteristics in the cited context

  • Simple 32-bit RISC-V implementation.
  • Simple single-issue design in the RVFI-DII integration discussion.
  • Used as a target in the TestRIG RVFI-DII ecosystem.
  • RVFI-DII support allowed instructions to be injected through a DII queue rather than fetched from the normal instruction cache in the described setup.

LINKED ENTITIES

3 links
TestRIG EVALUATES
In-Order Pipeline IMPLEMENTS
RVFI-DII USES

CITATIONS

4 sources
4 citations
[1] Piccolo is listed as a simple 32-bit RISC-V implementation in the TestRIG ecosystem, among implementations written in either SystemVerilog or Bluespec. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG participants require an RVFI-DII interface, an 8 MiB memory region at 0x80000000, access faults for other addresses, and reset to a known state on a reset DII packet. Randomized Testing of RISC-V CPUs using Direct
[3] RVFI-DII combines Direct Instruction Injection for instruction input with RVFI for trace output, supporting interactive verification. Randomized Testing of RISC-V CPUs using Direct
[4] Piccolo's simple single-issue design allowed the instruction cache to be replaced with a DII queue delivering one compressed or uncompressed instruction every cycle. Randomized Testing of RISC-V CPUs using Direct