In-Order Pipeline

Concept

An in-order pipeline is a processor microarchitecture style represented in the evidence by simple, single-issue RISC-V cores such as Flute and Piccolo, and by compact resource-constrained cores such as NoX. The cited material contrasts these designs with superscalar out-of-order processors and notes verification implications for pipelined implementations.

First seen 5/30/2026

Last seen 5/30/2026

Evidence 3 chunks

Wiki v1

WIKI

Overview

An in-order pipeline is a CPU pipeline organization discussed in the cited material as a comparatively simple processor design style, often appearing in single-issue RISC-V cores. The evidence contrasts such designs with superscalar out-of-order processors: Flute is described as a 5-stage in-order pipeline processor implementing RV64, while Toooba is described separately as a RISC-V 64-bit superscalar out-of-order processor.[c1]

Examples in the evidence

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NEIGHBORHOOD

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RELATIONSHIPS

2 connections

Piccolo ← implements 90% 2e

Piccolo is a simple 32-bit in-order pipeline processor.

Flute ← implements 100% 1e

Flute is a 5-stage in-order pipeline processor.

LINKED ENTITIES

2 links

Flute IMPLEMENTS Extracted graph relationship

Piccolo IMPLEMENTS Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Flute is a 5-stage in-order pipeline processor implementing RV64, contrasted with Toooba as a RISC-V 64-bit superscalar out-of-order processor. Randomized Testing of RISC-V CPUs using Direct

[2] Piccolo and Flute are described as simple single-issue designs in the RVFI-DII direct-instruction-injection discussion. Randomized Testing of RISC-V CPUs using Direct

[3] NoX is a compact open-source 32-bit RISC-V core with a 4-stage single-issue in-order pipeline with full bypass for resource-constrained MPSoC use. NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip

[4] For pipelined or superscalar microarchitectures, RVFI trace extraction may require preserving state until a commit/write-back stage that did not previously have access to the needed values. Randomized Testing of RISC-V CPUs using Direct

[5] Canceled or dropped instructions in a pipeline require synchronization for RVFI-DII; the Flute implementation carried sequence IDs through the pipeline so redirects worked naturally. Randomized Testing of RISC-V CPUs using Direct

[6] Covert-channel vulnerabilities can occur in average-complexity processors with in-order pipelining, not only in speculative or out-of-order high-end processors. Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking