Flute

Tool

Flute is a CTSRD-CHERI RISC-V processor implementation described in TestRIG evidence as a 5-stage in-order pipeline processor implementing RV64. In the TestRIG/RVFI-DII context, its simple single-issue design allowed the instruction cache to be replaced with a DII queue, and later RVFI-DII work on Flute used sequence IDs carried through the PC/pipeline to keep injected instructions synchronized with RVFI trace entries.

First seen 5/30/2026

Last seen 6/8/2026

Evidence 11 chunks

Wiki v1

WIKI

Overview

Flute is a RISC-V processor implementation in the CTSRD-CHERI ecosystem. The TestRIG paper identifies Flute as a 5-stage in-order pipeline processor implementing RV64 and lists its public repository as https://github.com/CTSRD-CHERI/Flute.^[1]

Role in TestRIG and RVFI-DII

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NEIGHBORHOOD

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RELATIONSHIPS

10 connections

TestRIG ← evaluates 100% 4e

TestRIG is used to validate correctness of the Flute CHERI implementation.

Physical Memory Protection uses → 80% 2e

Flute as a RISC-V microcontroller supports Physical Memory Protection.

UCAM-CL-TR-984 ← evaluates 100% 2e

The thesis evaluates the CHERI-extended Flute microcontroller including area, frequency, performance, and power overheads.

CHERI implements → 100% 2e

Flute is extended with CHERI modifications providing CHERI capability support.

RISC-V implements → 100% 2e

Flute is a RISC-V microcontroller from Bluespec.

micro-controller implements → 100% 2e

Flute is a microcontroller-class processor from Bluespec.

RVFI-DII uses → 90% 1e

Flute has been instrumented with RVFI-DII.

In-Order Pipeline implements → 100% 1e

Flute is a 5-stage in-order pipeline processor.

Bluespec uses → 100% 1e

Flute is implemented in Bluespec HDL.

merged register file implements → 100% 1e

Flute is one of the first CHERI implementations to support a merged register file.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

In-Order Pipeline IMPLEMENTS Extracted graph relationship

RVFI-DII USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] Flute is a 5-stage in-order pipeline processor implementing RV64, with repository https://github.com/CTSRD-CHERI/Flute. Randomized Testing of RISC-V CPUs using Direct

[2] TestRIG extends RVFI with Direct Instruction Injection; DII is used for instruction input, RVFI for trace output, and RVFI-DII supports interactive verification. Randomized Testing of RISC-V CPUs using Direct

[3] Flute's simple single-issue design allowed the instruction cache to be replaced by a DII queue that delivered one compressed or uncompressed instruction per cycle. Randomized Testing of RISC-V CPUs using Direct

[4] While adding RVFI-DII to Flute, the authors developed a sequence-ID design for synchronizing injected DII instructions with RVFI trace entries through pipeline redirects; a more capable DII unit was later backported to Flute. Randomized Testing of RISC-V CPUs using Direct