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Flute

Tool WIKI v1 · 5/30/2026

Flute is a CTSRD-CHERI RISC-V processor implementation described in TestRIG evidence as a 5-stage in-order pipeline processor implementing RV64. In the TestRIG/RVFI-DII context, its simple single-issue design allowed the instruction cache to be replaced with a DII queue, and later RVFI-DII work on Flute used sequence IDs carried through the PC/pipeline to keep injected instructions synchronized with RVFI trace entries.

Overview

Flute is a RISC-V processor implementation in the CTSRD-CHERI ecosystem. The TestRIG paper identifies Flute as a 5-stage in-order pipeline processor implementing RV64 and lists its public repository as https://github.com/CTSRD-CHERI/Flute.[1]

Role in TestRIG and RVFI-DII

In the TestRIG ecosystem, implementations are instrumented with RVFI-DII: Direct Instruction Injection (DII) supplies instruction input, while RVFI supplies trace output for interactive verification.[2]

Flute is discussed as one of the implementations used with TestRIG-style RVFI-DII instrumentation. The paper notes that the simple single-issue design of Piccolo and Flute made it possible to replace the instruction cache entirely with a DII queue delivering one instruction per cycle, either compressed or uncompressed.[3]

The paper also describes a synchronization issue for DII when instructions are canceled or dropped in the pipeline: RVFI-DII requires one RVFI trace entry for each DII instruction injected. While adding RVFI-DII to Flute, the authors developed a design that attaches a sequence ID to each RVFI instruction, carries it with the PC through the pipeline, and has Instruction Fetch actively request each instruction ID from the DII sequence so redirects work naturally.[4]

Implementation notes

  • Architecture class: RV64 processor implementation.[1]
  • Pipeline style: 5-stage in-order pipeline.[1]
  • Test instrumentation: RVFI-DII support was added to Flute; a more capable DII unit was later backported to Flute.[4]
  • DII strategy noted for Flute: because Flute is simple and single-issue, the instruction cache could be replaced with a DII queue delivering one instruction every cycle.[3]

[1]: Evidence chunk 29a08eb7-9b16-4f86-a71a-b495865d9f58. [2]: Evidence chunk fd70f40f-b468-4b11-b81a-2bb51b51a113. [3]: Evidence chunks 29a08eb7-9b16-4f86-a71a-b495865d9f58, fd70f40f-b468-4b11-b81a-2bb51b51a113. [4]: Evidence chunk fd70f40f-b468-4b11-b81a-2bb51b51a113.

LINKED ENTITIES

3 links
TestRIG EVALUATES
In-Order Pipeline IMPLEMENTS
RVFI-DII USES

CITATIONS

4 sources
4 citations
[1] Flute is a 5-stage in-order pipeline processor implementing RV64, with repository https://github.com/CTSRD-CHERI/Flute. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG extends RVFI with Direct Instruction Injection; DII is used for instruction input, RVFI for trace output, and RVFI-DII supports interactive verification. Randomized Testing of RISC-V CPUs using Direct
[3] Flute's simple single-issue design allowed the instruction cache to be replaced by a DII queue that delivered one compressed or uncompressed instruction per cycle. Randomized Testing of RISC-V CPUs using Direct
[4] While adding RVFI-DII to Flute, the authors developed a sequence-ID design for synchronizing injected DII instructions with RVFI trace entries through pipeline redirects; a more capable DII unit was later backported to Flute. Randomized Testing of RISC-V CPUs using Direct