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In-Order Pipeline

Concept WIKI v1 · 5/30/2026

An in-order pipeline is a processor microarchitecture style represented in the evidence by simple, single-issue RISC-V cores such as Flute and Piccolo, and by compact resource-constrained cores such as NoX. The cited material contrasts these designs with superscalar out-of-order processors and notes verification implications for pipelined implementations.

Overview

An in-order pipeline is a CPU pipeline organization discussed in the cited material as a comparatively simple processor design style, often appearing in single-issue RISC-V cores. The evidence contrasts such designs with superscalar out-of-order processors: Flute is described as a 5-stage in-order pipeline processor implementing RV64, while Toooba is described separately as a RISC-V 64-bit superscalar out-of-order processor.[c1]

Examples in the evidence

  • Flute: identified as a 5-stage in-order pipeline processor implementing RV64.[c1]
  • Piccolo and Flute: described as having a simple single-issue design in the context of RVFI-DII direct instruction injection work.[c2]
  • NoX: described in public context as a compact open-source 32-bit RISC-V core with a 4-stage single-issue in-order pipeline with full bypass, aimed at resource-constrained MPSoC edge-computing use cases.[c3]

Verification considerations

The TestRIG/RVFI-DII evidence notes that pipelined and superscalar microarchitectures can require additional care when extracting architectural trace information. In more complex RTL designs, including pipelined or superscalar microarchitectures, values needed for an RVFI report may have to be preserved until a commit/write-back stage that did not previously have access to them.[c4]

Direct Instruction Injection (DII) also has pipeline-specific synchronization issues. When instructions are dropped or canceled in the pipeline, RVFI-DII requires synchronization so that each injected DII instruction corresponds to a single RVFI trace entry. In the Flute implementation, the cited work reports carrying a sequence ID with each RVFI instruction through the pipeline, with Instruction Fetch requesting each instruction ID from the DII sequence; this allowed pipeline redirects to work naturally.[c5]

Security context

Public context also notes that covert-channel attacks are not limited to highly advanced speculative or out-of-order processors. One cited paper reports new classes of covert-channel attacks possible in average-complexity processors with in-order pipelining, a class described as mainstream in areas such as Internet-of-Things and autonomous systems.[c6]

Related implementations

  • Flute implements this concept in the provided related-entity data and is cited as a 5-stage in-order RV64 pipeline processor.[c1]
  • Piccolo is provided as a related implementation and is described in the evidence as a simple 32-bit implementation with a simple single-issue design.[c1][c2]

LINKED ENTITIES

2 links
Flute IMPLEMENTS
Piccolo IMPLEMENTS

CITATIONS

6 sources
6 citations
[1] Flute is a 5-stage in-order pipeline processor implementing RV64, contrasted with Toooba as a RISC-V 64-bit superscalar out-of-order processor. Randomized Testing of RISC-V CPUs using Direct
[2] Piccolo and Flute are described as simple single-issue designs in the RVFI-DII direct-instruction-injection discussion. Randomized Testing of RISC-V CPUs using Direct
[3] NoX is a compact open-source 32-bit RISC-V core with a 4-stage single-issue in-order pipeline with full bypass for resource-constrained MPSoC use. NoX: a Compact Open-Source RISC-V Processor for Multi-Processor Systems-on-Chip
[4] For pipelined or superscalar microarchitectures, RVFI trace extraction may require preserving state until a commit/write-back stage that did not previously have access to the needed values. Randomized Testing of RISC-V CPUs using Direct
[5] Canceled or dropped instructions in a pipeline require synchronization for RVFI-DII; the Flute implementation carried sequence IDs through the pipeline so redirects worked naturally. Randomized Testing of RISC-V CPUs using Direct
[6] Covert-channel vulnerabilities can occur in average-complexity processors with in-order pipelining, not only in speculative or out-of-order high-end processors. Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking