Piccolo

CodeArtifact

Piccolo is a simple 32-bit RISC-V implementation referenced in the TestRIG randomized CPU-testing work. In that context, Piccolo participates as an implementation that can be instrumented with RVFI-DII; its simple single-issue design allowed TestRIG researchers to replace the instruction cache with a DII queue delivering one compressed or uncompressed instruction per cycle.

First seen 5/27/2026

Last seen 6/3/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Piccolo is described in the TestRIG paper as one of several RISC-V CPU implementations used in the TestRIG ecosystem. The paper groups RVBS, Ibex, Piccolo, Flute, and Toooba as implementations written in either SystemVerilog or Bluespec, and specifically characterizes Ibex and Piccolo as simple 32-bit implementations. The paper also gives Piccolo's repository as https://github.com/CTSRD-CHERI/Piccolo. [C1]

Role in TestRIG

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NEIGHBORHOOD

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RELATIONSHIPS

4 connections

TestRIG ← evaluates 95% 8e

TestRIG has been used to test the Piccolo RISC-V processor.

RISC-V implements → 100% 5e

Piccolo is a simple 32-bit RISC-V implementation.

RVFI-DII implements → 90% 4e

Piccolo is instrumented with RVFI-DII for use in TestRIG.

RVFI-DII uses → 100% 3e

Piccolo is instrumented with RVFI-DII, with the cache replaced by a DII queue.

LINKED ENTITIES

3 links

TestRIG EVALUATES Extracted graph relationship

RISC-V IMPLEMENTS Extracted graph relationship

RVFI-DII USES Extracted graph relationship

CITATIONS

4 sources

4 citations — click to collapse

[1] Piccolo is listed with RVBS, Ibex, Flute, and Toooba as an implementation written in either SystemVerilog or Bluespec; Ibex and Piccolo are described as simple 32-bit implementations, and the paper gives the Piccolo GitHub repository URL. Randomized Testing of RISC-V CPUs using Direct

[2] TestRIG defines an ecosystem in which verification engines, models, and implementations can be interchangeable, and participants are expected to expose RVFI-DII, provide 8 MiB at 0x80000000, fault other addresses, and reset to a known state via a reset DII packet. Randomized Testing of RISC-V CPUs using Direct

[3] RVFI-DII combines DII for instruction input with RVFI for trace output, supports interactive verification, and can be added to existing RISC-V cores that implement RVFI by implementing DII. Randomized Testing of RISC-V CPUs using Direct

[4] Piccolo and Flute are described as simple single-issue designs for which the instruction cache could be replaced entirely with a DII queue delivering one compressed or uncompressed instruction every cycle. Randomized Testing of RISC-V CPUs using Direct