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Piccolo

CodeArtifact WIKI v1 · 5/27/2026

Piccolo is a simple 32-bit RISC-V implementation referenced in the TestRIG randomized CPU-testing work. In that context, Piccolo participates as an implementation that can be instrumented with RVFI-DII; its simple single-issue design allowed TestRIG researchers to replace the instruction cache with a DII queue delivering one compressed or uncompressed instruction per cycle.

Overview

Piccolo is described in the TestRIG paper as one of several RISC-V CPU implementations used in the TestRIG ecosystem. The paper groups RVBS, Ibex, Piccolo, Flute, and Toooba as implementations written in either SystemVerilog or Bluespec, and specifically characterizes Ibex and Piccolo as simple 32-bit implementations. The paper also gives Piccolo's repository as https://github.com/CTSRD-CHERI/Piccolo. [C1]

Role in TestRIG

TestRIG proposes a standardized verification ecosystem in which verification engines, models, and implementations can be interchangeable and improved independently. Implementations participating in this ecosystem are expected to expose an RVFI-DII interface, provide 8 MiB of memory at address 0x80000000, return access faults for other addresses, and support reset to a known state through a reset DII packet. [C2]

RVFI-DII integration

RVFI-DII combines RVFI trace output with Direct Instruction Injection input. The TestRIG paper states that DII is for instruction input, RVFI is for trace output, and RVFI-DII supports full interactive verification. Existing RISC-V cores that already implement RVFI can be augmented for TestRIG by implementing DII. [C3]

For Piccolo specifically, the paper notes that the simple single-issue design of Piccolo and Flute made it possible to replace the instruction cache entirely with a DII queue. That queue delivered one instruction per cycle, either compressed or uncompressed. This design choice is presented in contrast with the more complex superscalar Toooba integration, which required different handling around instruction picking and 16-bit fragments. [C4]

Technical significance

Within the provided evidence, Piccolo is significant mainly as a simple 32-bit RISC-V implementation that was amenable to RVFI-DII instrumentation. Its single-issue design simplified Direct Instruction Injection because the instruction cache could be replaced by a DII queue that supplied one instruction per cycle. [C1][C4]

LINKED ENTITIES

3 links
TestRIG EVALUATES
RISC-V IMPLEMENTS
RVFI-DII USES

CITATIONS

4 sources
4 citations
[1] Piccolo is listed with RVBS, Ibex, Flute, and Toooba as an implementation written in either SystemVerilog or Bluespec; Ibex and Piccolo are described as simple 32-bit implementations, and the paper gives the Piccolo GitHub repository URL. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG defines an ecosystem in which verification engines, models, and implementations can be interchangeable, and participants are expected to expose RVFI-DII, provide 8 MiB at 0x80000000, fault other addresses, and reset to a known state via a reset DII packet. Randomized Testing of RISC-V CPUs using Direct
[3] RVFI-DII combines DII for instruction input with RVFI for trace output, supports interactive verification, and can be added to existing RISC-V cores that implement RVFI by implementing DII. Randomized Testing of RISC-V CPUs using Direct
[4] Piccolo and Flute are described as simple single-issue designs for which the instruction cache could be replaced entirely with a DII queue delivering one compressed or uncompressed instruction every cycle. Randomized Testing of RISC-V CPUs using Direct