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RVFI-DII

Concept WIKI v1 · 5/27/2026

RVFI-DII is the TestRIG-compatible combination of RVFI-style per-instruction state observation with Direct Instruction Injection, used to compare RISC-V models, simulators, and simulated hardware implementations through generated instruction streams and trace comparison.

Overview

RVFI-DII refers to the instrumentation style used by TestRIG-compatible RISC-V models, simulators, and implementations: RVFI is used to observe architectural state changes after each instruction, while Direct Instruction Injection (DII) supplies the next instruction from the test harness rather than from program memory. The TestRIG paper describes this approach in the context of randomized RISC-V CPU testing and later refers to “models, simulators, and implementations supporting RVFI-DII.”

Role in TestRIG

TestRIG checks equivalence between a RISC-V model and an implementation under test by generating random instruction sequences, executing the same sequences on both sides, and comparing execution traces. This is tandem execution: it does not prove equivalence, but it can demonstrate divergence and is usable throughout development.

Within that workflow, RVFI provides the observation path: TestRIG uses the RISC-V Formal Interface standard to observe the state change after each instruction of the implementation under test. DII provides the injection path: instead of fetching the next instruction from memory at the address selected by the program counter, the test harness provides the next instruction regardless of the CPU’s program counter.

Execution and trace model

The evidence distinguishes normal execution from DII execution. In normal execution, the next instruction is fetched from program memory at an address determined by the program counter. Under DII, the test harness provides the next instruction directly. The resulting execution can be monitored as an RVFI trace and compared against traces from a model or other implementation.

Use cases and future direction

The TestRIG paper positions RVFI-DII as part of a practical verification workflow for RISC-V implementations, including executable formal models, software ISA simulators, and simulated execution of hardware designs rather than fabricated chips. The paper also identifies a future memory-concurrency testing direction in which RVFI-DII instruction streams with specified timestamps would be injected into multiple shared-memory cores to stimulate concurrency behaviors, requiring more advanced trace checking against memory-model semantics.

Relationship to related concepts

  • RVFI: RVFI-DII builds on RVFI for per-instruction observation of architectural state changes.
  • Direct Instruction Injection: RVFI-DII uses DII for harness-driven instruction supply.
  • TestRIG: TestRIG is the testing framework described as using RVFI and DII together, and the paper states that current TestRIG-compatible implementations and verification engines were collated into the open-source TestRIG repository.
  • Sail RISC-V Model: The TestRIG paper describes the standardized Sail RISC-V formal model as human-readable and usable for simulation and verification; TestRIG compares implementations against such models via generated instruction sequences and traces.

LINKED ENTITIES

11 links
TestRIG USES
Direct Instruction Injection IMPLEMENTS
RVFI EXTENDS
Sail RISC-V Model USES
RVBS USES
Piccolo USES
Flute USES
Toooba USES
spike USES
QEMU USES
Randomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES

CITATIONS

7 sources
7 citations
[1] TestRIG checks equivalence by generating random instruction sequences, executing them on a model and an implementation under test, and comparing execution traces; this can demonstrate divergence but does not prove equivalence. Randomized Testing of RISC-V CPUs using Direct
[2] TestRIG uses the RISC-V Formal Interface standard to observe the change in state after each instruction of the implementation under test. Randomized Testing of RISC-V CPUs using Direct
[3] Direct Instruction Injection provides the next instruction from the test harness regardless of the CPU program counter, unlike normal execution where the next instruction is fetched from program memory at an address determined by the program counter. Randomized Testing of RISC-V CPUs using Direct
[4] The TestRIG work compares executable formal models, software ISA simulators, and simulated execution of hardware designs rather than completed fabricated chips. Randomized Testing of RISC-V CPUs using Direct
[5] The paper refers to an array of models, simulators, and implementations supporting RVFI-DII. Randomized Testing of RISC-V CPUs using Direct
[6] A proposed future TestRIG direction is memory-model testing using RVFI-DII instruction streams injected with specified timestamps into multiple shared-memory cores, with checking against higher-level memory-model semantics. Randomized Testing of RISC-V CPUs using Direct
[7] The current TestRIG-compatible implementations and verification engines were collated into the open-source TestRIG repository. Randomized Testing of RISC-V CPUs using Direct