BSV-RVFI-DII Library

CodeArtifact

BSV-RVFI-DII is the cited RVFI-DII library/repository associated with TestRIG’s Direct Instruction Injection support. The TestRIG paper describes RVFI-DII as pairing DII instruction input with RVFI trace output for interactive verification, and says the RVFI-DII libraries provide reusable data structures, TCP-port connection support, and a mature DII unit for synchronizing injected instruction sequences with RVFI traces.

First seen 5/30/2026

Last seen 5/30/2026

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Overview

The BSV-RVFI-DII Library is the RVFI-DII library/repository cited by the TestRIG paper, which gives the repository URL as https://github.com/CTSRD-CHERI/BSV-RVFI-DII. In the paper’s terminology, RVFI-DII combines Direct Instruction Injection (DII) for instruction input with RVFI for trace output, enabling full interactive verification.

Role in RVFI-DII

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NEIGHBORHOOD

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RELATIONSHIPS

3 connections

Bluespec uses → 90% 2e

The BSV-RVFI-DII library is implemented in Bluespec.

RVFI-DII implements → 95% 1e

The BSV-RVFI-DII library provides a Bluespec implementation of the RVFI-DII interface.

Randomized Testing of RISC-V CPUs using Direct Instruction Injection ← introduces 85% 1e

The paper presents the BSV-RVFI-DII library as a reusable component for RVFI-DII instrumentation.

LINKED ENTITIES

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RVFI-DII IMPLEMENTS Extracted graph relationship

Bluespec USES Extracted graph relationship

Randomized Testing of RISC-V CPUs using Direct Instruction Injection INTRODUCES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] The TestRIG paper cites the BSV-RVFI-DII repository at https://github.com/CTSRD-CHERI/BSV-RVFI-DII. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[2] RVFI-DII uses DII for instruction input and RVFI for trace output, supporting full interactive verification. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[3] The authors distribute data structures and libraries in several languages to facilitate RVFI-DII connections over TCP ports. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[4] A more capable DII unit is available in the RVFI-DII libraries and uses sequence IDs to keep injected instructions synchronized with RVFI trace entries through pipeline redirects. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[5] The paper shows a Bluespec implementation of a DII interface that receives a reset command followed by a sequence of instructions. Randomized Testing of RISC-V CPUs using Direct Instruction Injection

[6] DII directly specifies the expected instruction sequence in the output trace and does not associate instructions with memory addresses, simplifying sequence generation and shrinking. Randomized Testing of RISC-V CPUs using Direct Instruction Injection